============================================================================= Intel(R) Server Board SE7501WV2 BIOS RELEASE NOTES ============================================================================= INTEL Enterprise Platform & Services Marketing Intel Corporation 2111 N.E. 25th Avenue, Hillsboro, OR 97124 USA ============================================================================= DATE: December 7, 2005 TO: Intel server platform SE7501WV2 customers SUBJECT: BIOS Release Notes: BIOS Production Release P43 (build 0260) ============================================================================= Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Intel is a registered trademark of Intel Corporation. *Other names and brands are the property of their respective owners. Copyright (C) 2001-2005 Intel Corporation. ============================================================================= ABOUT THIS RELEASE ============================================================================= Release # : P43 Version # : 43.00 Build # : 0260 Build Stamp : SWV25.86B.0260.P43.0512071840 Build Date : 7 December 2005 ============================================================================= BIOS COMPONENTS/CONTENTS ============================================================================= Processors supported: Intel(R) Xeon(TM) Processors with 512KB L2 Cache and No L3 Cache, 1M L3 Cache, or 2M L3 Cache. Microcode update versions: CPUID (Stepping) Microcode Rev. ----- ---------- -------------- 0F24h (B0) 1F (M02F241F) 0F27h (C1) 38 (M02F2738) 0F29h (D1) 2D (M02F292D) 0F25h (M0) 29 (M01F2529) System Hardware Configurations Supported: SE7501WV2 (all fabs) ============================================================================= SYSTEM FIRMWARE REQUIREMENTS/REVISIONS ============================================================================= BMC FW (Current ver.) : 1.20 [1.23 for TIGPR2U Carrier Grade Server] FRU/SDR (Current ver.) : 5.6.B [LP-5.6.D for TIGPR2U Carrier Grade Server] HSC (Current ver.) : 0.06 (SR2300 Chassis) 0.08 (SR1300 Chassis) On-Board Component Option ROM Versions: -------------------------------------- SCSI Controller : Adaptec 7902 SCSI : 4.30S2 ATA RAID Controller : Promise PDC20277 : 2.30.0140.15 Video Controller : ATI Rage XL VGA : 09A GR 4.332 NIC Controller : Intel Pro/1000 NIC : 1.2.26 ============================================================================= IMPORTANT INSTALLATION NOTES ============================================================================= IMPORTANT NOTES: 1. This build does not require a CMOS clear if installed over an SE7501WV2 BIOS release P10 or later. CMOS -must- be cleared for installation over a BIOS earlier than P10. CMOS Clear is ALWAYS advised as a safety measure. 2. SE7501WV2 BIOS Update is not compatible with Windows 98 or Windows XP bootable diskettes. Please use a DOS 6.22 bootable diskette or a ROM-DOS bootable diskette. 3. Firmware must be updated before BIOS. If it is not, the BIOS update may not work. Refer to the System Firmware Requirements section above. UPDATE INSTRUCTIONS: These instructions do not apply when running the update directly from the Software Update Package Menu. In that case, instructions displayed on the screen should be followed. The instructions below only apply when updating from a BIOS update disk. 1. Note the settings of the SETUP parameters. Do this as a safety measure even if you do not intend to clear CMOS. Enter SETUP by hitting the F2 key during boot. Write down the settings for all Setup parameters, so that at the end of the BIOS update process you can restore them. 2 Download the BIOS from the Intel Support website. Insert a bootable diskette into drive "A:". Run 'BIOS.EXE a:' to expand the BIOS onto the bootable floppy in "A:". 3. Place the bootable floppy containing the BIOS into drive "A:" of the system that you want to upgrade, and boot the system from the diskette drive. 4. Update with the IFLASH program -- it is HIGHLY recommended that you update the BootBlock as well as the BIOS> 4.1 Type 1 at the DOS prompt BIOS option menu to update both automatically. -or- 4.2 Type 2 to start IFLASH in interactive mode. Update and reboot the system by following the menu prompts in IFLASH. The interactive mode allows you to update the User Logo or User Binary area, if necessary. (You'll know if you need to do this!) 5. The update will show two progress bars, one after the other. DO NOT DO ANYTHING TO INTERRUPT THE UPDATE! After the second progress bar has reached 100 percent, the system will reboot (typically under 3 minutes). 6. Once the update is complete, proceed to clear CMOS if you plan to do so. Then enter Setup by pressing the F2 key during boot up. Once in Setup, you can press the F9 to set the parameters back to default values. Re-enter the values you wrote down at the beginning of this process. If you do not set the CMOS values back to defaults using the F9 key or by clearing CMOS, the system may behave erratically if the CMOS layout has changed in the new BIOS version. NOTE: You may encounter a CMOS Checksum error or other problem after reboot. Try shutting down the system and booting up again. CMOS checksum errors require that you enter Setup, check your settings, save your settings with F10, and exit Setup. CLEARING CMOS (JUMPER): 1. Power down the system and disconnect AC power. 2. Move the CMOS Clear jumper (J1D4) from BMC Control position (pins 1-2) to the Force Erase position (pins 2-3). 3. Power up the system and allow BIOS to boot. A message will be displayed indicating "NVRAM Cleared by Jumper". If applicable, enter BIOS Setup by pressing F2 and change any BIOS user settings; press F10 to Save Changes and Exit. 4. Power down the system and disconnect AC power. 5. Move the CMOS Clear jumper (J1D4) back to BMC Control position (pins 1-2). 6. Power up the system and boot normally. CLEARING CMOS (FRONT PANEL): 1. Press and hold the front panel reset button for 4+ seconds. 2. Continue to hold the reset button and press the front panel power button 3. Release the reset and power button at the same time. 4. The server board will appear to boot in a normal manner but should display an "NVRAM Cleared by BMC" message during the boot. ============================================================================= BIOS RECOVERY NOTES ============================================================================= 1. BIOS Recovery requires that you have a copy of the BIOS on a diskette, prepared the same way as for a normal update. 2. Power down the system and disconnect AC power. Move the BIOS Recovery Jumper (J1D4) from the normal position (pins 9-10) to the Recovery position (pins 10-11). 3. Place the BIOS Update diskette in drive "A:", reconnect power and boot the system. 4. As the system begins to boot, you will hear one BEEP. There will be no display. DO NOT INTERRUPT THE RECOVERY. At the end of recovery, there will be a double BEEP indicating success. 5. Power down the system and disconnect AC power. Move the BIOS Recovery Jumper (J1D4) back to the normal position (pins 9-10). 6. Reconnect power and boot normally. ============================================================================= KNOWN ISSUES/WORKAROUNDS ============================================================================= #19075 - Adaptec OpROM will only recognize 6 SCSI Channels on WV533. The latest version of the Adaptec SCSI Option ROM will only scan for boot drives on the first 6 channels in Adaptec SCSI controllers, including both the onboard SCSI controller and all add-in Adaptec SCSI adapters combined. -- Workaround: (1) Place the drive from which the OS is to be booted on one of the first six Adaptec SCSI channels, or (2) place the boot drive on a non-Adaptec SCSI or IDE connection, or (3) disable the SCSI boot scan on SCSI channels which do not have a bootable drive installed them. ________________________________________ #20419 - Problems Creating & Booting USB Disk-on-Key. Some USB Disk-on-Keys (USB Flash Drives) will not boot on WV533. The same USB Keys will boot on some other server systems. Also, a USB Key which has been partitioned on a Windows OS as an emulated hardfile could not be made bootable even by running DOS FDISK and SYS on WV533. FDISK was not able to build a bootable MBR & Partition Table, even though the USB Key was recognized as a hardfile when the system booted. A USB Key which had been cleared to blank space (unpartitioned, unformatted) was recognized in POST as an HDD -- but was not accessible to FDISK from DOS booted from diskette. The key could not be partitioned and formatted into a bootable DOS system. -- Workaround: Boot to ROMDOS, MSDOS, or PCDOS on a system which can forced to recongnize the USB Key as hardfile, then partion it using FDISK. When a USB Key is partitioned, a partition is set Active, then formatted and SYS'ed from "real" DOS (not Windows) on a system that "understands" it as a hardfile emulation (or can have HDD emulation forced), there is no problem booting the USB Key on WV533. In fact, after the initial partitioning, the key can be reformatted and used with Windows-derived DOS systems and will boot sucessfully. ________________________________________ #23115 - The Intel POST Logo Screen disappears after a User Binary module is installed. This problem was caused by the BIOS code overflowing into the space reserved for the User Binary. As a result, when the User Binary module is installed, it overwrites the logo graphics file header at the bottom end of the BIOS. This means that when the BIOS goes to display the logo during POST, it does not find a graphics file header, and is unable to display the logo. This issue only affects users who install a User Binary module to insert their own code to be executed during POST. The POST display is only affected for users who display the default Intel Logo Screen during POST. It does not affect a custom User Logo which has been installed, and it does not affect the text-mode Diagnostic Screen which is displayed for boot with Console Redirection enabled. -- Workaround: A customer who does install a User Binary module and also wants to have the Intel Logo Screen displayed during POST can install the Intel Logo as a custom "User Logo" file. A User Logo display is unaffected by this problem. An installable version of the Intel Logo Screen is available by request. ============================================================================= ========================== ABOUT THIS RELEASE =========================== ============================================================================= P43-0260 Production Release: --Features Added: BIOS ID updated to Production Release P43-0260. C01-0259 Release Candidate: -------------------- --Features Added: Accumulated fixes since the WV533 P39-0250 release have been integrated. See "Issues Resolved" below for details. ________________________________________ #16878 - Updated onboard Promise ATA RAID firmware to rev. 2.30.0140.15. See "Issues Resolved" below for problem resolved. ________________________________________ #20211 - Updated embedded Intel Boot Agent to version 1.2.26. This is a maintenance update. There were no major fixes or problems resolved. ________________________________________ --Issues Resolved: #15077 - Boot order changes when MegaRAID 493 card present: when you create or delete a logical drive in a MegaRAID 493 card RAID Array or when any boot device is removed, the Boot Order becomes set to an unexpected setting. This fix maintains the boot order as it was set in the previous boot when deleting a logical drive or removing any other boot device. ________________________________________ #16878 - Cannot build with console redirection enabled. The specific symptom observed was a system hang when building or rebuilding an ATA RAID array with Console Redirection active. The onboard Promise ATA RAID BIOS was fixed to correct this. The RAID array build problems in the onboard ATA RAID BIOS were caused by a problem in servicing the timer interrupt. Interrupts were improperly reenabled while still servicing the timer interrupt, allowing "stacked interrupts" (another interrupt during servicing an interrupt) which could cause stack overflows and system hangs. These resulted in failures in the ATA RAID BIOS or in Serial Console Redirection, or in other modules during (and after) POST. With Fault Resilient Boot enabled, these hangs could be observed as FRB errors recorded in the System Event Log (SEL). ________________________________________ #17403 - Connecting USB floppy causes reordering of default boot: When connecting a USB floppy or any other boot device, Boot Order may become random. This fix maintains the previous boot order with the added boot device at the end of the main boot order, if the device's IPL Category was not present in the previous boot. If the device's IPL category was present in the previous boot, the added boot device will be added at the end of its IPL device category without affecting the device category's position in the main boot order. ________________________________________ #19831 - 16M PCI card not allocated correctly in bridge settings. Card was initializing too slowly to respond to first pass for bridge resource determination. Added ~1 sec delay before scanning PCI system for bus number assignment and resource requirements. ________________________________________ #19998 - Front Panel CMOS Clear resets BIOS security settings without requiring password. In addition, it is possible to do a Front Panel CMOS Clear... (1) Even when the FP Power Button is disabled, and/or (2) Secure Boot is enabled, and (3) A/C Link is set to "Always On", ...following either a Windows Shutdown or an A/C power failure (or unplugging the power supply). The power-on vulnerability has been fixed, and now the FP CMOS Clear is not allowed to reset the BIOS Security settings for the following options (CMOS Clear by jumper will reset these settings): FP Power Button Inhibit NMI Control AC Link (Powerfail) Policy Post Error Pause Boot Password Secure Boot Secure Mode Timeout Secure Mode Hotkey Video Blanking Floppy Drive Write Protect (OEM-specific visibility) HDD Boot Sector Write Protect Four fixes were required in the BIOS code: Fix #1 - Ignore Front Panel CMOS Clear when FP Power button disabled Fix #2 - FP CMOS Clear does not clear Security Sceen settings Fix #3 - CMOS Clear does not clear passwords - preserve PWD status Fix #4 - Corrupt CMOS init (per Diagnostic Byte) should clear passwords ________________________________________ #20278 - Setup Option To Include All Processor Threads In MP Table - A new Setup option, "HT Technology in MPS" was added to the Processor menu. When it is enabled along with HyperThreading, the MPS table will include entries for secondary processor threads as well as primary processor threads. This is for support of older pre-ACPI Operating Systems, where in some cases, primarily on heavily loaded systems, it may improve performance. ________________________________________ #20910 - Error in BMC Timestamp Fix Caused Memory Corruption - Problem was a failure in the fix for the BMC Timestamp problem (#19816). Failure was corrected. ________________________________________ #22809 - Minor correction to the Setup Helps. The Help for Extended Memory Test Step Size was incorrectly labeled as "Text" so it did not display. ________________________________________ #22812 - Flash Update Procedure Error Handling - the current Flash Update procedure does not check for errors in the BAT file that drives it. Even if the Boot Block update fails, the BAT files will go ahead and flash in the BIOS update. If the latter operation is successful, the system will reboot with no indication that the update operation encountered problems. The IFLASH program does return an ERRORLEVEL value, which can be checked to determine whether the update operation succeeded. The automatic update BAT file has been changed to do that check, and to make execution of the second update operation conditional on the success of the first update. ============================================================================= ======================== PREVIOUS RELEASES ============================== ============================================================================= P42-0257 Production Release: This release was an interim HotFix with specific fixes to PCI bus initialization. Those fixes have been incorporated into the P43 Production Release BIOS. This build was based on BIOS P39-0250. ============================================================================= P41-0256 Production Release: This release was an interim HotFix with specific fixes to Boot Order functions. Those fixes have been incorporated into the P43 Production Release BIOS. This build was based on BIOS P39-0250. ============================================================================= P40-0251 Production Release: This release was an interim HotFix with specific fixes to Front Panel CMOS Clear operation. Those fixes have been incorporated into the P43 Production Release BIOS. This build was based on BIOS P39-0250. ============================================================================= P39-0250 Production Release: --Features Added: BIOS ID updated to Production Release P39-0250. --Issues Resolved: #19816 - BIOS sets BMC Timestamp incorrectly one day behind. BIOS was calculating the 32-bit BMC timestamp incorrectly by one day for synchronization at boot, resulting in BMC date one day behind system date as recorded in SEL entries. This calculation has been corrected. ============================================================================= P38-0249 Production Release: This release was an OEM BIOS with OEM-specific features. It was based on BIOS P37-0246. ============================================================================= P37-0246 Production Release: --Features Added: BIOS ID updated to Production Release P37-0246. --Issues Resolved: #19359 - Windows 2003 Server Device Manager shows only two processors in a dual processor HyperThreaded system. This was due to mismatch in Processor IDs between the Processor and Local APIC definitions. These ID's have been changed to match. ============================================================================= P36-024 Production Release: This release was an OEM BIOS with OEM-specific features. It was based on BIOS P34-0239. ============================================================================= P35-0241 Production Release: This release was an OEM BIOS with OEM-specific features. It was based on BIOS P34-0239. ============================================================================= P34-0239 Production Release: --Features Added: BIOS ID updated to Production Release P34-0239. C01-0233 Release Candidate: -------------------- --Features Added: Accumulated fixes since WV533 P28-0218 release have been integrated. See below for details. ________________________________________ #18736 - Updated embedded Intel Boot Agent to version 1.2.22. ________________________________________ #18708 - Add new Prestonia CPU Microcode for D1 and M0 steppings. Fixes for Xeon Processor Errata P72 & P76 (see Specification Update). Xeon DP D1 stepping processor microcode updated to rev 2Dh (M02F292D). Xeon DP M0 stepping processor microcode updated to rev 29h (M01F2529). ________________________________________ --Issues Resolved: #14700 - 5V Riser Card Issue when Installing LSI MegaRAID U320-1 Card. On a 5V Riser limited to PCI 33MHz, LSI MegaRAID U320-1 card caused bus to be incorrectly configured to 66MHz. PCI Bus mode/speed logic has been changed to first check PCIXCAP, and if PCIXCAP shows PCI, ignore the rest of that bus scan since initial HW bus setting for mode and speed will be correct. ________________________________________ #15026 - Add-in Card generates PCI memory conflict. #15832: Older Customer Card Requires Additional Reset Recovery Time. These two cards take more time to respond after a PCI Reset is done. The code originally did the minimum specified reset time and delay after PCI Reset. Additional time delays have been inserted into the code which resets the PCI bus to set the bus mode and speed, in two areas. First, the delay between asserting and deasserting secondary bus reset was increased from 1ms to 100ms. Second, after deassertion of RST#, the Trhfa delay was changed to two seconds, for any bus speed. [This fix was taken from Bryson, where it has been working consistently for some time.] ________________________________________ #15209 - Logitech Internet Navigator USB keyboard sees PS/2 mouse as legacy keyboard: POST message "Legacy Keyboard..Detected" displayed even though there is no PS/2 Keyboard connected. Fixed by testing for a legacy KB presence before displaying the message. ________________________________________ #15459 - Issues with PCI adapter card population order. When a PCI-X 66MHz card was positioned lower on riser than a PCI-only card, the bus would be configured incorrectly to PCI-X 66MHz. The logic has been changed to determine PCI configuration first by the hardware PCIXCAP signal. Also, the "early escape" when a PCI-X 66MHz card was found in the bus scan has been removed, and the full scan is completed in case there is a card that incorrectly claims PCI-X capability. ________________________________________ #15744 - PCI-X Backward compatibility issue. A PCI 33MHz/64bit card was failing due to bus configuration to 66MHz, even though the HW configuration was correctly set initially. The logic now uses the HW mode/speed bus configuration if PCIXCAP signal indicates PCI mode. ________________________________________ #15783 - System hangs when NIC cable is removed in DOS. Added routine to shut off the NIC interrupts so when we boot DOS there is no unserviced interrupt happening. ________________________________________ #16737, #16738 - Minor changes to synchronize BIOS code modules between base WV533 BIOS and OEM versions. ________________________________________ #17252 - OEM Name on Diagnostic/Redirection Screen: The first line of the text-mode Diagnostic/Redirection POST screen will display the Manufacturer Name from the BMC FRU "MN" field. If the MN field is defaulted to "Intel", the name will not be displayed. ________________________________________ #17257 Make AC Link Setting Available In BIOS Setup for UPS Support. AC Link policy for WV533 defaults to "Last State" after reboot from powerfail. This is a problem for UPS users -- if UPS does shutdown after powerfail, system will not power on when power returns. Power policy set via controls to BMC will be overwritten at boot, since BIOS sends AC Link setting to BMC during POST. This fix makes the "After Powerfail" option available to set AC Link policy explicitly for all WV533 systems. ________________________________________ #17740 - PCI Cards with P2P Bridges Cause Bus Configuration Errors. An adapter with a PCI-PCI bridge on the card, installed in the Full- Height riser, could cause a card on the Low Profile riser to hang. The bus numbering was assumed to be bus 3 and bus 4 on the P64H2, but that was not true if a bridge card was present on bus 3, so bus numbers are now read from the P64H2 bridge registers. ________________________________________ #18615 - SMBIOS Onboard Devices FW Revs Incorrect. The Firmware for onboard NIC and SCSI controller had outdated revision levels listed in the SMBIOS table. These were corrected to current levels. ============================================================================= P33-0237 Production Release: This release was an interim HotFix BIOS with updated processor microcode, replaced by BIOS P34-0239. It was based on BIOS P28-0218. ============================================================================= P32-0231 Production Release: This release was an interim HotFix BIOS with OEM-specific features which were later incorporated into BIOS P34-0239. It was based on BIOS P28-0218. ============================================================================= P31-0230 Production Release: This release was an interim HotFix with OEM-specific fixes which will be incorporated into a future general release. It was based on BIOS P28-0218. ============================================================================= P30-0229 Production Release: This release was an interim HotFix with OEM-specific fixes which will be incorporated into a future general release. It was based on BIOS P28-0218. ============================================================================= P29-0225 Production Release: This release was an interim HotFix BIOS with updated processor microcode, replaced by BIOS P34-0239. It was based on BIOS P28-0218. ============================================================================= P28-0218 Production Release: --Features Added: BIOS ID updated to Production Release P28-0218. --Issues Resolved: #16996 Boot Hangs With 2 Adapters on Full-Height Riser: 2 PCI-X adapters in any positions on the full-height riser caused a hang at POSTcode 5Eh (PCI initialization). Tracker 15138/15139 fix backed out, was causing the hangs. --Features Removed: #15459 - Issues with PCI adapter card population order: The algorithm to calculate PCI bus speed was fixed to find out the correct bus speed. ============================================================================= P27-0217 Production Release: This release was an interim HotFix with OEM-specific fixes which will be incorporated into a future general release. It was based on BIOS P26-0214. It has been superceded by BIOS P30-0229. ============================================================================= P26-0214 Production Release: --Features Added: BIOS ID updated to Production Release P26-0214. --Issues Resolved: #15138/15139 fix backed out. Caused problems. --Features Removed: #15138/15139 - Custom Defaults/Guaranteed Boot. ============================================================================= P25-0213 Production Release: --Features Added: BIOS ID updated to Production Release P25-0213. C01-0212 Release Candidate: -------------------- --Issues Resolved: #14906: User Logo lost during boot. This was caused by a failure in the Fault Tolerant Update. The failure has been corrected. #15953: User Binary Erases Default Logo. This was caused by an incorrect Flash memory configuration definition. ============================================================================= P24-0211 Production Release: --Features Added: BIOS ID updated to Production Release P24-0211. C02-0206 Release Candidate: -------------------- --Features Added: #16028 - M0 stepping processor microcode updated (M01F251A.PDB). --Issues Resolved: #15138/15139 - Residual Password and Console Redirection settings restored during load custom defaults. C01-0201 Release Candidate: -------------------- --Features Added: Trackers fixed in P17, P18, P19, P21, P22, D03-200, D16-0199 are integrated for quarterly release, as listed below in the "Bug Fixes" section. ________________________________________ Updated embedded Intel Boot Agent to version 1.2.16p2. ________________________________________ Updated embedded Adaptec 7902 SCSI/HostRAID Option ROM to version 4.30s2. ________________________________________ --Issues Resolved: #15099 - System fails to boot in certain memory configurations: This was due to memory plus PCI configurations which exceeded available variable MTRRs. This build has late POST error reporting along with a "failsafe boot" fallback which allows the system to display Error 124 and pause for user response, then boot if possible. The fallback configuration allocates the maximum 2GB PCI space in a single MTRR to allow fallback boot. In addition to the error handling and fallback configuration, this build also has changed the granularity (size increments) of PCI space allocation from 128M to 256M. This eliminates most error cases caused by running out of variable MTRRs. Also, memory register setup errors were corrected for certain cases where installed memory was less than 4GB, but PCI space overlapped installed memory and required remapping. Memory sizing errors for these same cases were also corrected. ________________________________________ #15168 - No POST error when MPS Table cannot be built: In conjunction with late POST error handling added in #15099 above, error message 123 with POST pause was added for cases where the MPS Table has not been built or copied to F000 space. ________________________________________ #15198 - Logic Errors in WV533 PCI Memory Allocation Code: Logic errors in passing the size required for PCI space were corrected. Other errors were also addressed in fixing #15099. ________________________________________ #15138 - Saved custom defaults not restored as default setting automatically on TIGPR2U: Fix was added to the code to load custom default values if CMOS battery fails. ________________________________________ #15139 - Langley PR - Need for guaranteed Boot: The fix for 15138 fixes this as well. ________________________________________ #15457 - IBA EEPROM Corruption: Erroneous EEPROM checksum error messages could be displayed if adapter is in use by BIOS LAN console during Boot Agent initialization. Modified EEPROM read/write code to disable processor interrupts while accessing the EEPROM. Updated version of IBA (Intel Boot Agent) with fix - version 1.2.16p2. ________________________________________ #15331 - SE7501WV2 Boot Agent won't boot to PXE server: Updated IBA (Intel Boot Agent) to version 1.2.16p2 (from 1.1.08). ________________________________________ #15288 - SE7501WV2 BIOS Boot Agent Needs To Be Updated To Allow Windows RIS: Updated IBA (Intel Boot Agent) to version 1.2.16p2 (from 1.1.08). ________________________________________ #15113 - SMI Timeout Errors after exit from Setup: Bryson SMI fix added -- re-issue the software SMI if it does not get serviced the first time. In addition, shut off USB Legacy SMI generation when "Save and Exit" is chosen from Setup. This stops the SMI hang that occurs when leaving Setup. ________________________________________ #15459 - Issues with PCI adapter card population order: The algorithm to calculate PCI bus speed was fixed to find out the correct bus speed. ________________________________________ #15435 - SuSE 8.2 and 9.0 fail in a HostRAID config: Latest Adaptec oprom version 4.30S2 updated. ________________________________________ #15451 - Stack corruption issue in the ReportCPUMismatch routine: Stack balanced in the erroneous path. ________________________________________ #15026 - Add-in card generates PCI memory conflict: The Intervoice card took more time to respond for PCI cycles. A Delay was introduced after PCI bus reset. ________________________________________ #11349 -Disabling embedded NIC ports we receive a POST error message - PXE-E01: BIOS cannot run its server management stack if onboard NICs are disabled. The server management code is not run if both NICs are disabled. ________________________________________ #15568 - SYSID test fails - reports wrong information: The SYSID pointer was calculated wrongly -- fixed. ============================================================================= P23-0207 Production Release: This release was an interim HotFix BIOS with OEM-specific features which were later incorporated into BIOS P34-0239. It was based on BIOS P16-0190. ============================================================================= P22-0198 Production Release: This release was an interim HotFix BIOS with OEM-specific fixes which were later incorporated into BIOS P24-0211. It was based on BIOS P16-0190. ============================================================================= P21-0197 Production Release: This release was an interim HotFix BIOS with OEM-specific fixes which were later incorporated into BIOS P24-0211. It was based on BIOS P15-0183. ============================================================================= P20-0196 Production Release: This release was an OEM BIOS with OEM-specific features. It was based on BIOS P16-0190. It was later superceded by BIOS P35-0241. ============================================================================= P19-0195 Production Release: This release was an interim HotFix BIOS with OEM-specific fixes which were later incorporated into BIOS P24-0211. It was based on BIOS P17-0192. ============================================================================= P18-0193 Production Release: This release was an interim HotFix BIOS with OEM-specific fixes which were later incorporated into BIOS P24-0211. It was based on BIOS P11-0175. ============================================================================= P17-0192 Production Release: This release was an interim HotFix BIOS with OEM-specific fixes which were later incorporated into BIOS P24-0211. It was based on BIOS P15-0183. It was superceded by BIOS P19-0195. ============================================================================= P16-0190 Production Release: --Features Added: BIOS ID updated to Production Release P16-0190. C01-0187 Release Candidate: -------------------- --Issues Resolved: #14787 - Fixed POST hang when rebooting mutiple times. ============================================================================= P15-0183 Production Release: --Features Added: BIOS ID updated to Production Release P15-0183. C01-0180 Release Candidate: -------------------- --Features Added: New Microcodes updated. --Issues Resolved: #14393 - 3.06/533 Processors Show 'Max Speed' and 'Curent Speed' Slightly Slower. ________________________________________ #14822 - Added speeds 3.2 and 3.4 for upcoming processor releases. ________________________________________ #14767 - 41003S2 SCSI Option ROM added to BIOS build. ________________________________________ #14801 - Mixed processor steppings code updated for M0 processors. ________________________________________ #14789, 14880 - Updated BIOS update code for processors as shown above. ________________________________________ #14855 - Sony SDX-420C & SDX-520C ATAPI Tape Drives fixed to work in U-DMA and PIO modes. ________________________________________ #14850 - BIOS logo incorrectly displayed after CMOS clear ________________________________________ Corrected BIOS SMM error table to send correct information to BMC to log SBE. ============================================================================= P14-0179 Production Release: This release was an interim HotFix BIOS with OEM-specific fixes which were later obsoleted by BIOS P25-0213. It was based on BIOS P12-0177. ============================================================================= P13-0178 Production Release: --Features Added: BIOS ID updated to Production Release P13-0178. #14801 - M0 stepping of Intel Xeon Processors (2/2.4/2.66/2.8GHz) is made possible in this bios. --Issues Resolved: Processor String speed fixed in Setup. ============================================================================= P12-0177 Production Release: --Features Added: BIOS ID updated to Production Release P12-0177. C01-0176 Release Candidate: -------------------- --Issues Resolved: #14788 - Incorrect SMBIOS Cache Reference when L3 Absent. ________________________________________ #14787 - Improper L3 Cache Initialization. ============================================================================= P11-0175 Production Release: --Features Added: BIOS ID updated to Production Release P11-0175. --Issues Resolved: #14726 - Failure to display Logo (Splash Screen) when booting. ============================================================================= P10-0174 Production Release: --Features Added: BIOS ID updated to Production Release P10-0174. ________________________________________ Added support for M0 processors (both with and without 1M L3 cache). ________________________________________ Added support for mixed cpu steppings. ________________________________________ --Issues Resolved: Fix for MCH Errata3 - system hung after asynchronous reset to DIMM. Fixed issue where some DIMMS could get locked up in a bad state, causing ECC errors During POST. This needed a DC power cycle to get the DIMM back to normal working order. ________________________________________ #13722 - Fixed issue where NIC1 can not PXE Boot if the device that is higher in boot priority is connected ________________________________________ #14393 - Added support for 3.06 Gig processors to SMBIOS tables. ________________________________________ #14678 - BIOS P08 Not Allowing SMP Kernel to Load with RH AS 2.1 ES ________________________________________ #13798 - DIMM error occurred on POST with Samsung 1GB during AC or DC cycling test. ________________________________________ Fix to make PCI slots on 1U systems match the value returned by PCI BIOS function B1h, sub-function 0Eh (Get PCI IRQ routing option), previously it just returned the # of slots in the system. ________________________________________ Added fix to open up more F000 space by removing code for non-Xeon processors. This may fix the MPS table issue when certain NICs are added. ============================================================================= P09-0169 Production Release: --Features Added: BIOS ID updated to Production Release P09-0169. C01-0167 Release Candidate: -------------------- --Features Added: Added support for D1 processor. --Issues Resolved: Fixed .ASL code so the Online update code would work, and still pass WHQL testing. ============================================================================= P08-0165 Production Release: --Features Added: BIOS ID updated to Production Release P08-0165. --Issues Resolved: Removed ICH3 RTC workaround code from SMM code. This code was causing the system to hang after recording an ECC SBE. ============================================================================= P07-0160 Production Release: --Features Added: BIOS ID updated to Production Release P07-0160. C02-0160 Release Candidate: -------------------- --Issues Resolved: Fix the problem where PCIX cards are plugged into a 5V riser card. They should run at 33MHz, BIOS was running them at 66MHz. C01-0156 Release Candidate: -------------------- --Features Added: Upgrade BBS code to version 3.21 ________________________________________ Updated code needed to operate with the F24 B0 stepping processor. ________________________________________ (OEM Specific) Added special OEM Host RAID support. ________________________________________ (OEM Specific) Needed to describe BMC address ranges and OEM BMC IRQ in ASL code to pass HCT 11.x tests. ________________________________________ (OEM Specific) Wake from S5: OEM requested wake from S5 support for PME/WOL/WOR. ________________________________________ --Issues Resolved: (OEM Specific) Fixed code for OEM where the System Reconfigured SEL wasn't being logged when exiting Setup and saving changed. ________________________________________ (OEM Specific) OEM's virtual LCD message "Prepare to Boot" was being partially overwritten by the POST progress code 0xAE. The is resolved by moving initLcdBeforeBoot to be the last call in the post table. ________________________________________ Updated FRBDisable strings from 'Disable' to 'Disabled' per the EPS. ________________________________________ Changed Type 8 structure strings for Serial ports from COM A/Serial Port B to Serial Port 1/Serial Port 2. ________________________________________ Add _ to the start of the OEM strings that were space characters. This is done so the macro won't strip out the space chars. We need the padding to allow GPNV updates of type 11 to work. ________________________________________ Changed default of Q_SYSMGMT_CONTINUE_SERIAL_REDIR token to 0. This prevents the console redirection disable escape sequence from being sent to the keyboard. ________________________________________ Added code to populate the SSID when the Adaptec RAID option is selected. ________________________________________ HCT 11.x complained about I/O Apic memory assignments not being defined. Changed code to not include these ranges when defining the PCI hole. ________________________________________ Fixed BIOS LED codes for 3 Memory beep codes to follow the EPS. ________________________________________ Add code to determine if serial ports are disabled when selecting setup items BIOS Redirection Port and ACPI Redirection Port. If the serial port is not disabled, don't display it and if both are disabled, gray the option. ________________________________________ When CMOS is cleared via the front panel switches, don't display message to power down the system and clear the CMOS jumper when exiting setup. ________________________________________ ABS 2.0: Don't enable boot monitor timer on boot to floppy or CDROM drive. ________________________________________ ABS 2.0: Selecting Reset config data in setup doesn't generate a system re-configured SEL event. Also, when exiting setup saving changes, system re-configured event isn't logged. ________________________________________ Add code to allow PXE boot from NIC 1 even if NIC 2 is connected. ________________________________________ Needed to describe BMC address ranges in ASL code to pass HCT 11.x tests. ________________________________________ Late POST Timeout: The late post timeout functionality wasn't implemented to behave the same as the OS boot and PXE boot timeout. This functionality is required for Telco. ________________________________________ Fixed 32bit PCI code that returns the PCI IRQ routing information. ESI should return the pointer to the table, but the upper 16 bits were incorrect. Changed to code to properly compute the physical address of the IRQ table. ________________________________________ Add MCA handler for processors. This is a requirement for processors with Hyperthreading Technology. See Netburst BWG update for details. ============================================================================= P06-0119 Production Release: --Features Added: BIOS ID updated to Production Release P06-0119. C03-0118 Release Candidate: -------------------- --Issues Resolved: Debugged error logging of DIMM ordering rules. Single Row DIMMs must be populated furthest away from the MCH. Appropriate POST error message will be displayed telling the user which DIMMs need to be swapped. ============================================================================= P05-0117 Production Release: --Features Added: BIOS ID updated to Production Release P05-0117. C02-0117 Release Candidate: -------------------- --Issues Resolved: Debugged error logging of DIMM ordering rules. Single Row DIMMs must be populated furthest away from the MCH. If they are not, then a 3 beep POST error will occur with POST DIAG LEDs = 08h. C01-0117 Release Candidate: -------------------- --Issues Resolved: Update to memory reference code revision 1.02. ============================================================================= P04-0116 Production Release: --Features Added: BIOS ID updated to Production Release P04-0116. C02-0116 Release Candidate: -------------------- --Issues Resolved: #13678: BIOS doesn't lock down the primary flash partition, it only locks it. Changed code to lock down the BIOS in the primary partition so it can't be overwritten. ============================================================================= P03-0115 Production Release: --Features Added: BIOS ID updated to Production Release P03-0115. C01-0115 Release Candidate: -------------------- --Issues Resolved: (OEM Specific) #13475: Setup Viewer I/F incorrect. ________________________________________ (OEM Specific) #13477: Some SELs aren't generated. ________________________________________ #13471: Error message not displayed during POST for different speed processors. ________________________________________ #13472: FRB Policy set to "Retry 3 Times" in Setup causes the system to not complete POST. ________________________________________ #13474: When CMOS jumper is set, Setup shows installed DIMMs as "Not Installed." ________________________________________ Added string translations for BMC related strings in Setup. ============================================================================= P02-0111 Production Release: --Features Added: BIOS ID updated to Production Release P02-0111. C01-0105 Release Candidate: -------------------- --Issues Resolved: #13380: Added a POST screen message to display FSB speed since both 400MHz and 533MHz processors can run in the system. This will give the end user feedback on which processors are installed. ________________________________________ Update to memory reference code rev. 1.01 ________________________________________ #13131: System ACPI Power State is not reflected at the time of S1 and S4 Sleep. Removed the checks for EC ASL code for board revision ID. The board revision ID code was only needed for WV400. ________________________________________ #12922: Post 12 hang on power-cycle. Added code to not access the NIC on the first boot when determining OEM/Intel behaviour. This is causing a hang when the P64H2 PLL isn't synched. ________________________________________ #13329: Need to change MAX length of strings for DMI Type1. Changed default string length from 32 chars to 40 chars. ________________________________________ New ATA Promise option ROM version 2.0.0140.8. ============================================================================= P01-0094 Production Release: --Features Added: BIOS ID updated to Production Release P01-0094. --Issues Resolved: #13061: Remove SMBUS I/O ranges from motherboard resources in the ASL code. Win2K was showing I/O conflicts with the SMBUS device. ________________________________________ #13036: Remove BMC ports from the motherboard resources ASL code. It is breaking an OEM's IPMI driver. ________________________________________ #12735: WV(533) fails to boot with ATA option selected in BIOS. Added new ATA Promise ROM that correctly handles EBDA. C02-0089 Release Candidate: -------------------- --Issues Resolved: Updated to memory reference code revsion 1.0. #13007: 2.88 floppy option not working correctly. ________________________________________ #12953: I15_F87 reports system issues. Both of these issues were caused by changing the build to make BIOS use fast gate A20 instead of gate A20. Backing the change out because it is too risky at this point in the project. ________________________________________ #12962: BIOS not sending MUX switch notification when DPC connects via Modem/Dir. Reserved bit in command are now being used. BIOS now maskes the bit. ________________________________________ #12999: Fixed 115.2K-baud rate when using ACPI serial redirection. ________________________________________ Changed code to preserve port 74h, the alias of port 70h and restore that value to port 70h during the POST INT8 interrupt handler. ________________________________________ Update string translations. ________________________________________ C01-0081 Release Candidate: -------------------- --Issues Resolved: Added new Promise RAID option ROM. It is FastTrak TX2000 Lite BIOS Version 2.30.0140.11 ________________________________________ #12338: Added 38.4K-baud rate to the Console Redirection options in Setup. ________________________________________ #12785: When FRB2 is disabled in BIOS setup, always get FRB2 error. Code was added to handle this case. ________________________________________ #12821: Changed the code for the P64H2 PLL work around to not access any devices behind the P64H2 until after the system has been reset. ________________________________________ #12823: BIOS should display physical processors. Changed the code to follow Netburst Architecture BWG rev 1.6 to only display physical processors during POST. ________________________________________ #12837 & 12835. Fixes for rolling BIOS implementation. BIOS should roll back if BIOS checksum is bad. Also, update both bootblock and BIOS when executing 1.bat ________________________________________ #12851: Unable to apply CPU microcode updates with CHECKUP6. Code was debugged and now microcode updates applied to the BIOS with CHECKUP6 get loaded into all processors. ________________________________________ #12881: Intel RAID cards not working on Westville 533 (BIOS B05 +). This was due to the Intel RAID card going into protected mode and not returning to big real mode. The fix is to go back into big real mode immediatly after option ROMs have executed. ________________________________________ #12882: BIOS doesn't enable front side bus parking in UP configurations. Changed code to follow the E7501 MCH BIOS specification update revision 0.71 to enable front side bus parking when the system has a UP configuration. ________________________________________ Use Port 92h for A20 (fast gate A20). The build disabled the flag that BIOS uses to determine whether to use the keyboard controller or port 92h. ============================================================================= REFERENCE MATERIAL ============================================================================= Intel(R) Server Platform SE7501WV2 Technical Product Specification (TPS) Technical Support: http://support.intel.com [END OF RELEASE NOTES]