DTD Parameter
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Description
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DTD Type
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DTD Settings Flags
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This section allows you to set flags for Interlace,
Vertical Sync Polarity, Horizontal Sync Polarity, and Blank Sync Polarity.
Each field in this section is described below.
Note:
These flags are Intel®
EMGD-specific and do not correspond to VESA 3.0 flags.
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• Interlaced Display
— Check for Interlaced
— Cleared for Non-interlaced
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EMGD, VESA, Hardware, Simple, Mode Lines
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• Vertical Sync
Polarity
— Active Low (Default)
— Active High
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EMGD, VESA, Hardware, Mode Lines
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• Horizontal Sync
Polarity
— Active Low (Default)
— Active High
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EMGD, VESA, Hardware, Mode Lines
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• Blank Sync Polarity
— Active Low (Default)
— Active High
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EMGD, VESA, Hardware, Simple, Mode Lines, EDID Block
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Pixel Clock
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Pixel clock value in KHz. Range 0-0x7fffffff.
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EMGD, VESA, Hardware
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Horizontal Sync Offset (Front Porch) in pixels
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Specifies the amount of time after a line of the
active video ends and the horizontal sync pulse starts (Horizontal Front
Porch). Range 0-1023 [10 bits].
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EMGD
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Horizontal Sync Pulse Width (Sync Time) in pixels
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Width of the Horizontal Sync Pulse (Sync Time) which
synchronizes the display and returns the beam to the left side of the
display. Range 0-1023 [10 bits].
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EMGD, VESA
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Horizontal Blank Width (Blank Time) in pixels
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This parameter indicates the amount of time it takes
to move the beam from the right side of the display to the left side
of the display (Blank Time). During this time, the beam is shut off,
or blanked. Range 0-4095 [12 bits].
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EMGD, VESA
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Horizontal Active (Width) in pixels
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Number of pixels displayed on a horizontal line
(Width). Range 1-32767 [15 bits].
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EMGD, VESA, Hardware, Simple
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Horizontal Sync Start in pixels
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This parameter specifies the start of the horizontal
active time.
Range 0-40957.
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VESA, Hardware
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Horizontal Sync End in pixels
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This parameter specifies the end of the horizontal
active time.
Range 0-49148.
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Hardware
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Horizontal Blank Start in pixels
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This parameter specifies the start of one line of
the video and margin period. Range 0-32766.
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VESA
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Horizontal Blank End in pixels
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This parameter specifies the end of one line of
the video and margin period. Range 0-65533.
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Hardware
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Refresh in Hz
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Also known as the Vertical Refresh, the rate the
full display updates. Standard refresh rates are 50Hz, 60Hz, 75Hz, and
85Hz.
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Simple
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Vertical Sync Offset (Front Porch) in lines
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Specifies the amount of time after last active line
of video ends and vertical sync pulse starts (Vertical Front Porch).
Range 0-4095 [12 bits].
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EMGD
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Vertical Sync Pulse Width (Sync Time) in lines
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Specifies the Width of the Vertical Sync Pulse which
synchronizes the display on the vertical axis and returns the beam to
the top, left side of the display. Range 0-63 [6 bits].
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EMGD, VESA
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Vertical Blank Width (Blank Time) in lines
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The amount of time for the complete vertical blanking
operation to complete. It indicates the time it takes to move the beam
from the bottom right to the top, left side of the display (Blank Time).
During this time, the beam is shut off, or blanked. Range 0-4095 [12
bits].
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EMGD, VESA
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Vertical Active (Height) in lines
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The number of active lines displayed (Height). Range
1-4095 [12 bits].
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EMGD, VESA, Hardware, Simple
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Vertical Sync Start in lines
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This parameter specifies the start of the vertical
sync. Range 0-4157.
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VESA, Hardware
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Vertical Sync End in lines
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This parameter specifies the end of the vertical
sync. Range 0-4220.
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Hardware
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Vertical Blank Start in lines
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This parameter specifies the start of display vertical
blanking including margin period. Range 0-4094.
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VESA
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Vertical Blank End in lines
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This parameter specifies the end of vertical blanking.
Range 0-8189.
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Hardware
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Mode Lines
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The Mode Lines are a video timing spec used by X.Org.
The X.Org timing setting for Mode Lines is “name” I A B C
D E F G H. For example: “640x480@8bpp” 25.175 640 672 728
816 480 489 501 526.
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Mode Lines
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EDID Block
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The EDID Block is the detailed timing section (18
bytes) of the basic 128-byte EDID data structure. The detailed timing
section starts at 36h of the 128-byte EDID data structure. Enter the
EDID block 1 byte at a time. Example:
a0 0f 20 00 31 58 1c 20 d2 1a 14 00 f6 b8 00 00 00 18
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EDID Block
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