Configuration Options [eliminate]
The table below describes available Intel® EMGD settings. The gray rows are block headings and the non-gray rows that follow each heading are settings within the block. Some of these block headings are contained within prior block headings.
Parameter Configuration Format
Optional keyword used to specify which configuration is used. The config ID specified here must match one of the configuration IDs defined with CED. If this keyword is omitted, all configurations specified in the config file are used. Note that this keyword is not required for Linux OS and VBIOS configurations. |
||
A quoted string used to identify the origin of the .bin or .inf file. |
||
Used to configure initial state of attached displays. 2 – Clone. Primary and secondary displays enabled and configured with separate timing pipes. This allows different timings to be applied to each display. Resolutions can be different on both displays. 8 – Extended. Configures separate pipes to allow primary and secondary displays to have different resolutions and display different content. Upon first boot after the driver installation, this option will enable only the primary display, as the extended modes must be enabled in the operating system (i.e., Extended Desktop in the Display Properties sheet within Microsoft Windows). |
||
Enable or disable Display Detection. Note that this parameter must be Enabled in order to use COMMON_TO_PORT values. Default is 0. Please see Display Detect Operation for detailed information on this parameter. |
||
PortOrder must be specified as a quoted string containing five digits. The valid values are: |
Search order for detecting attached displays for the Display Detection feature. When Display Detection is enabled, the PortOrder determines which display is primary and which display is secondary. The port search order can be specified to ensure the port device (SDVO device) is found, based on the system integrator’s routing choices. Default ordering is chosen by specifying zeros in the PortOrder keys. Default ordering is chipset specific; see Default Search Order. Please see Display Detect Operation for more information on using PortOrder in combination with the Display Detect feature. |
|
clonewidth – 800, cloneheight - 600 clonewidth – 1024, cloneheight - 768 |
||
Typical refresh rates (expressed in Hz): |
||
When checked, this enables overlay blending with the framebuffer on both display outputs when display mode resolution is 32-bit XRGB. |
||
This parameter enables the Intel® EMGD to pass the DIB call back to the OS. This is required in certain circumstances to improve performance. |
||
This block contains settings for the Video BIOS. Note that you only need to specify the parameters you are actually using. You do not need to specify all the parameters in this block. If you omit any parameters, the vbios uses the default values. |
||
Maps the ports from the system BIOS to a port number used by the graphics hardware. Please see Section 3.5.5, “Configuring the Video BIOS and EFI” on page 44 for more information on this parameter. Note that the displaydetect parameter must be set to Enabled in order for the COMMON_TO_PORT values to be used. |
||
greater than 0 - enable and display POST message for the specified number of seconds |
Enables or disables the POST (Power On Self Test) message. When you specify a value greater than 0, the message is displayed for the specified number of seconds. For example: This enables the POST message and displays it for approximately 5 seconds. The maximum value that can be entered here is 65535. The default is 1, enable and display the POST message for approximately 1 second. |
|
This string appears on the display when the post_display_msg is enabled and the VBIOS starts up. The maximum string length is 100 characters. The default is " " (two double quotes with a single space in between). |
||
This string appears on the display when the post_display_msg is enabled and the VBIOS starts up. The maximum string length is 80 characters. The default is " " (two double quotes with a single space in between). |
||
This string appears on the display when the post_display_msg is enabled and the VBIOS starts up. The maximum string length is 80 characters. The default is " " (two double quotes with a single space in between). |
||
This string appears on the display when the post_display_msg is enabled and the VBIOS starts up. The maximum string length is 80 characters. The default is " " (two double quotes with a single space in between). |
||
This parameter allows you to enable or disable the five System BIOS 15h interrupt hooks. The value must be 5 digits in length. Each digit is associated with one of the five System BIOS interrupt 15h hooks as shown below (left to right) 1 - 5F31h, POST Completion Notification Hook 2 - 5F33h, Hook After Mode Set 3 - 5F35h, Boot Display Device Hook 4 - 5F36h, Boot TV Format Hook 5 - 5F38h, Hook Before Set Mode (Please see Intel® 5F Extended Interface Functions for more information on 5F functions.) The value of each digit must be a 0 or a 1 as follows: 0 - disable a System BIOS 15h hook 1 - enable a System BIOS 15h hook Enables 5F31h, 5F33h, and 5F38h hooks only. The 5F35h and 5F36h hooks are disabled. |
||
Default: 0 – disabled, allow centering and add compatibility modes |
When this option is enabled it DISABLES centering. Also, depending on the combination of “edid” + “user-dtd” + connected hardware, Intel® EMGD will add missing compatibility modes (6x4, 8x6, 10x7& 12x10) via centering. Use this option to disable this feature. |
|
This option provides flexibility for enabling or disabling the display tuning functionality of the SDVO Clipped Display software workaround. |
||
Internal timing value that the graphics driver expects for the SDVO Clip software workaround algorithm. |
||
Valid values (specified in hex): bit 0=0: Do not use built-in standard =1: Use driver built-in standard bit 1=0: Do not use EDID block. =1: Use EDID block and filter (Bit 1 not applicable to edid_not_avail.) |
These two parameters are used to control the available timings for any display. edid_avail is used when EDID values are read from the display. If an attempt to read EDID from the display fails or the edid parameter is set to 0, then the driver uses the edid_not_avail flags. The value for both parameters must be specified as a decimal or hex value, e.g., “3” or “0x3” edid_avail: “3” sets Bit 0 = 1, Bit 1 = 1, Bit 2 =0 (Use driver built-in standard timings and EDID block and filter modes.) edid_not_avail: “1” sets Bit 0 = 1, Bit 1 = 0, Bit 2 = 0. (Use driver-built-in standard timings.) |
|
The GPIO pin pair used on the I2C bus to read and write to SDVO device registers. |
||
I2C device address for reading and writing device registers. The device address should be in 8-bit format with the 7-bit slave address assigned to its bits 7:1 and bit 0 set to 0. |
||
I2C device address for reading EDID data from display through the DDC bus. |
||
Note: The only supported parameter for internal LVDS is 1 – Port Driver |
Instructs which backlight method is required for the panel attached to the given port. If zero is supplied, or the key is not present, then no backlight control is provided. |
|
Units of 1ms => the limit specified in your hardware specifications. For example, the maximum for the CH7307 is 409 ms. |
(T1) Time delay between VDD active, and SDVO clock/data active. Zero indicates no delay required. |
|
(T2) Time delay between SDVO clock/data active and backlight enable. |
||
(T3) Time delay between backlight disable and SDVO clock/data inactive. |
||
(T4) Time delay between SDVO clock/data inactive and VDD inactive. |
||
Valid ICH GPIO pin, 0 indexed |
||
GPIO connection for backlight power on/off sequencing signal. |
||
This entry is needed when GMCH is selected as backlight control method. |
||
This entry is needed when GMCH is selected as backlight control method. |
||
Denotes a Detailed Timing Descriptor (DTD) block. Settings in this section, except for the flags parameter, correspond to the Detailed Timing Block described in the VESA standard “Extended Display Identification Data Standard”, Version 3, November 13, 1997. |
||
0 - vertical sync polarity active low 1 - vertical sync polarity active high 0 - horizontal sync polarity active low 1 - horizontal sync polarity active 0 - blank sync polarity active high |
Interlace, Horizontal polarity, Vertical polarity, Sync Configuration, etc. Note that these flags are Intel® EMGD specific and do not correspond to VESA 3.0 flags. For example, to set Interlaced with Horizontal Sync Polarity high (bits 31 and 26), then the flags value = 0x84000000. (Binary = 10000100 00000000 00000000 00000000) |
|
Attribute values that are specific to the SDVO device for the port. See Port Driver Attributes for specific attribute IDs and associated values. |
||
Both the Attribute ID and its value should be specified in decimal. For example, to set brightness to 50, you specify |