web_CreatingCustDTD

Creating a New Customized DTD

CED Lite allows you to create Dynamic Timings Definitions (DTD) for EDID-less displays or displays for which you do not want to use the display's EDID settings. In either of those cases, you can create your own DTD using the steps below. Any DTDs you create will be available for all configurations. Otherwise you can use one of the standard DTDs included in CED Lite.

On the Custom DTD tab you can choose the DTD type from the drop-down list and then set parameters for your choice. Parameters for each type are described in the following sections.

Select the DTD Type that most closely aligns with your display parameters. Options are:

EMGD Parameters – The EMGD Parameters are the same as the current PCF/CED DTD parameters.

VESA Parameters – The VESA Parameters allow the user to create a DTD from a VESA monitor timing standard.

Hardware Parameters – The Hardware Parameters are the parameters that are used by Intel® EMGD.

Simple Parameters – The Simple Parameters (CVT Standard) is a process for computing standard timing specifications. The method for developing Reduced Blanking timings is not included.

Mode Lines – The Mode Lines are a video timing spec used by X.Org. The X.Org timing setting for Mode Lines is “name” I A B C D E F G H. For example: “640x480@8bpp” 25.175 640 672 728 816 480 489 501 526.

EDID Block – The EDID Block is the detailed timing section (18 bytes) of the basic 128-byte EDID data structure. The detailed timing section starts at 36h of the 128-byte EDID data structure. Enter the EDID block 1 byte at a time. Example:
a0 0f 20 00 31 58 1c 20 d2 1a 14 00 f6 b8 00 00 00 18

Each of these DTD types may have additional parameters, which are described in the table below.

 

Intel® EMGD DTD Setting Options

DTD Parameter

Description

DTD Type

DTD Settings Flags

This section allows you to set flags for Interlace, Vertical Sync Polarity, Horizontal Sync Polarity, and Blank Sync Polarity. Each field in this section is described below.

 

Note: These flags are Intel® EMGD-specific and do not correspond to VESA 3.0 flags.

 

Interlaced Display

— Check for Interlaced

— Cleared for Non-interlaced

EMGD, VESA, Hardware, Simple, Mode Lines

Vertical Sync Polarity

— Active Low (Default)

— Active High

EMGD, VESA, Hardware, Mode Lines

Horizontal Sync Polarity

— Active Low (Default)

— Active High

EMGD, VESA, Hardware, Mode Lines

Blank Sync Polarity

— Active Low (Default)

— Active High

EMGD, VESA, Hardware, Simple, Mode Lines, EDID Block

Pixel Clock

Pixel clock value in KHz. Range 0-0x7fffffff.

EMGD, VESA, Hardware

Horizontal Sync Offset (Front Porch) in pixels

Specifies the amount of time after a line of the active video ends and the horizontal sync pulse starts (Horizontal Front Porch). Range 0-1023 [10 bits].

EMGD

Horizontal Sync Pulse Width (Sync Time) in pixels

Width of the Horizontal Sync Pulse (Sync Time) which synchronizes the display and returns the beam to the left side of the display. Range 0-1023 [10 bits].

EMGD, VESA

Horizontal Blank Width (Blank Time) in pixels

This parameter indicates the amount of time it takes to move the beam from the right side of the display to the left side of the display (Blank Time). During this time, the beam is shut off, or blanked. Range 0-4095 [12 bits].

EMGD, VESA

Horizontal Active (Width) in pixels

Number of pixels displayed on a horizontal line (Width). Range 1-32767 [15 bits].

EMGD, VESA, Hardware, Simple

Horizontal Sync Start in pixels

This parameter specifies the start of the horizontal active time.
Range 0-40957.

VESA, Hardware

Horizontal Sync End in pixels

This parameter specifies the end of the horizontal active time.
Range 0-49148.

Hardware

Horizontal Blank Start in pixels

This parameter specifies the start of one line of the video and margin period. Range 0-32766.

VESA

Horizontal Blank End in pixels

This parameter specifies the end of one line of the video and margin period. Range 0-65533.

Hardware

Refresh in Hz

Also known as the Vertical Refresh, the rate the full display updates. Standard refresh rates are 50Hz, 60Hz, 75Hz, and 85Hz.

Simple

Vertical Sync Offset (Front Porch) in lines

Specifies the amount of time after last active line of video ends and vertical sync pulse starts (Vertical Front Porch). Range 0-4095 [12 bits].

EMGD

Vertical Sync Pulse Width (Sync Time) in lines

Specifies the Width of the Vertical Sync Pulse which synchronizes the display on the vertical axis and returns the beam to the top, left side of the display. Range 0-63 [6 bits].

EMGD, VESA

Vertical Blank Width (Blank Time) in lines

The amount of time for the complete vertical blanking operation to complete. It indicates the time it takes to move the beam from the bottom right to the top, left side of the display (Blank Time). During this time, the beam is shut off, or blanked. Range 0-4095 [12 bits].

EMGD, VESA

Vertical Active (Height) in lines

The number of active lines displayed (Height). Range 1-4095 [12 bits].

EMGD, VESA, Hardware, Simple

Vertical Sync Start in lines

This parameter specifies the start of the vertical sync. Range 0-4157.

VESA, Hardware

Vertical Sync End in lines

This parameter specifies the end of the vertical sync. Range 0-4220.

Hardware

Vertical Blank Start in lines

This parameter specifies the start of display vertical blanking including margin period. Range 0-4094.

VESA

Vertical Blank End in lines

This parameter specifies the end of vertical blanking. Range 0-8189.

Hardware

Mode Lines

The Mode Lines are a video timing spec used by X.Org. The X.Org timing setting for Mode Lines is “name” I A B C D E F G H. For example: “640x480@8bpp” 25.175 640 672 728 816 480 489 501 526.

Mode Lines

EDID Block

The EDID Block is the detailed timing section (18 bytes) of the basic 128-byte EDID data structure. The detailed timing section starts at 36h of the 128-byte EDID data structure. Enter the EDID block 1 byte at a time. Example:
a0 0f 20 00 31 58 1c 20 d2 1a 14 00 f6 b8 00 00 00 18

EDID Block

See also DTD Example Specifications.




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Revised June 20, 2011