5 #include "qm_ss_gpio.h"
7 static void (*callback[QM_SS_GPIO_NUM])(
void *data, uint32_t int_status);
8 static void *callback_data[QM_SS_GPIO_NUM];
10 static uint32_t gpio_base[QM_SS_GPIO_NUM] = {QM_SS_GPIO_0_BASE,
15 uint32_t int_status = 0;
16 uint32_t controller = gpio_base[gpio];
18 int_status = __builtin_arc_lr(controller + QM_SS_GPIO_INTSTATUS);
21 callback[gpio](callback_data[gpio], int_status);
24 __builtin_arc_sr(int_status, controller + QM_SS_GPIO_PORTA_EOI);
29 ss_gpio_isr_handler(QM_SS_GPIO_0);
34 ss_gpio_isr_handler(QM_SS_GPIO_1);
40 uint32_t controller, reg_ls_sync_;
42 QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
43 QM_CHECK(cfg != NULL, -EINVAL);
45 controller = gpio_base[gpio];
47 #if (HAS_SS_GPIO_CLK_ENABLE)
53 __builtin_arc_sr(BIT(0), controller + QM_SS_GPIO_CLKEN);
56 __builtin_arc_sr(0xFFFFFFFF, controller + QM_SS_GPIO_INTMASK);
58 __builtin_arc_sr(cfg->
direction, controller + QM_SS_GPIO_SWPORTA_DDR);
59 __builtin_arc_sr(cfg->
int_type, controller + QM_SS_GPIO_INTTYPE_LEVEL);
61 controller + QM_SS_GPIO_INT_POLARITY);
62 __builtin_arc_sr(cfg->
int_debounce, controller + QM_SS_GPIO_DEBOUNCE);
64 #if (HAS_SS_GPIO_INTERRUPT_BOTHEDGE)
66 controller + QM_SS_GPIO_INT_BOTHEDGE);
73 reg_ls_sync_ = __builtin_arc_lr(gpio_base[gpio] + QM_SS_GPIO_LS_SYNC);
74 __builtin_arc_sr(reg_ls_sync_ | BIT(0),
75 controller + QM_SS_GPIO_LS_SYNC);
77 __builtin_arc_sr(cfg->
int_en, controller + QM_SS_GPIO_INTEN);
79 __builtin_arc_sr(~cfg->
int_en, controller + QM_SS_GPIO_INTMASK);
87 QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
88 QM_CHECK(pin <= QM_SS_GPIO_NUM_PINS, -EINVAL);
89 QM_CHECK(state != NULL, -EINVAL);
92 ((__builtin_arc_lr(gpio_base[gpio] + QM_SS_GPIO_EXT_PORTA) >> pin) &
101 QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
102 QM_CHECK(pin <= QM_SS_GPIO_NUM_PINS, -EINVAL);
104 val = __builtin_arc_lr(gpio_base[gpio] + QM_SS_GPIO_SWPORTA_DR) |
106 __builtin_arc_sr(val, gpio_base[gpio] + QM_SS_GPIO_SWPORTA_DR);
114 QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
115 QM_CHECK(pin <= QM_SS_GPIO_NUM_PINS, -EINVAL);
117 val = __builtin_arc_lr(gpio_base[gpio] + QM_SS_GPIO_SWPORTA_DR);
119 __builtin_arc_sr(val, gpio_base[gpio] + QM_SS_GPIO_SWPORTA_DR);
128 QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
131 val = __builtin_arc_lr(gpio_base[gpio] + QM_SS_GPIO_SWPORTA_DR);
132 val ^= (-state ^ val) & (1 << pin);
133 __builtin_arc_sr(val, gpio_base[gpio] + QM_SS_GPIO_SWPORTA_DR);
140 QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
141 QM_CHECK(port != NULL, -EINVAL);
143 *port = (__builtin_arc_lr(gpio_base[gpio] + QM_SS_GPIO_EXT_PORTA));
150 QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
152 __builtin_arc_sr(val, gpio_base[gpio] + QM_SS_GPIO_SWPORTA_DR);
157 #if (ENABLE_RESTORE_CONTEXT)
163 QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
164 QM_CHECK(ctx != NULL, -EINVAL);
166 controller = gpio_base[gpio];
169 __builtin_arc_lr(controller + QM_SS_GPIO_SWPORTA_DR);
171 __builtin_arc_lr(controller + QM_SS_GPIO_SWPORTA_DDR);
172 ctx->
gpio_inten = __builtin_arc_lr(controller + QM_SS_GPIO_INTEN);
173 ctx->
gpio_intmask = __builtin_arc_lr(controller + QM_SS_GPIO_INTMASK);
175 __builtin_arc_lr(controller + QM_SS_GPIO_INTTYPE_LEVEL);
177 __builtin_arc_lr(controller + QM_SS_GPIO_INT_POLARITY);
178 ctx->
gpio_debounce = __builtin_arc_lr(controller + QM_SS_GPIO_DEBOUNCE);
179 ctx->
gpio_ls_sync = __builtin_arc_lr(controller + QM_SS_GPIO_LS_SYNC);
189 QM_CHECK(gpio < QM_SS_GPIO_NUM, -EINVAL);
190 QM_CHECK(ctx != NULL, -EINVAL);
192 controller = gpio_base[gpio];
194 __builtin_arc_sr(0xffffffff, controller + QM_SS_GPIO_INTMASK);
196 controller + QM_SS_GPIO_SWPORTA_DR);
198 controller + QM_SS_GPIO_SWPORTA_DDR);
199 __builtin_arc_sr(ctx->
gpio_inten, controller + QM_SS_GPIO_INTEN);
201 controller + QM_SS_GPIO_INTTYPE_LEVEL);
203 controller + QM_SS_GPIO_INT_POLARITY);
204 __builtin_arc_sr(ctx->
gpio_debounce, controller + QM_SS_GPIO_DEBOUNCE);
205 __builtin_arc_sr(ctx->
gpio_ls_sync, controller + QM_SS_GPIO_LS_SYNC);
206 __builtin_arc_sr(ctx->
gpio_intmask, controller + QM_SS_GPIO_INTMASK);
qm_ss_gpio_state_t
GPIO SS pin states.
uint32_t gpio_swporta_ddr
Port A Data Direction.
uint32_t gpio_debounce
Debounce Enable.
uint32_t int_type
Interrupt type, 0b: level; 1b: edge.
qm_ss_gpio_t
Sensor Subsystem GPIO.
uint32_t int_polarity
Interrupt polarity, 0b: low, 1b: high.
uint32_t int_en
Interrupt enable.
uint32_t gpio_int_polarity
Interrupt Polarity.
int qm_ss_gpio_save_context(const qm_ss_gpio_t gpio, qm_ss_gpio_context_t *const ctx)
Save SS GPIO context.
uint32_t gpio_intmask
Interrupt Mask.
int qm_ss_gpio_set_pin(const qm_ss_gpio_t gpio, const uint8_t pin)
Set a single pin on a given SS GPIO port.
uint32_t int_bothedge
Interrupt on rising and falling edges.
QM_ISR_DECLARE(qm_ss_gpio_0_isr)
ISR for GPIO 0 error interrupt.
int qm_ss_gpio_clear_pin(const qm_ss_gpio_t gpio, const uint8_t pin)
Clear a single pin on a given SS GPIO port.
SS GPIO port configuration type.
int qm_ss_gpio_set_pin_state(const qm_ss_gpio_t gpio, const uint8_t pin, const qm_ss_gpio_state_t state)
Set or clear a single SS GPIO pin using a state variable.
uint32_t gpio_inttype_level
Interrupt Type.
int qm_ss_gpio_write_port(const qm_ss_gpio_t gpio, const uint32_t val)
Get SS GPIO port values.
int qm_ss_gpio_read_port(const qm_ss_gpio_t gpio, uint32_t *const port)
Get SS GPIO port values.
int qm_ss_gpio_set_config(const qm_ss_gpio_t gpio, const qm_ss_gpio_port_config_t *const cfg)
Set SS GPIO port configuration.
int qm_ss_gpio_read_pin(const qm_ss_gpio_t gpio, const uint8_t pin, qm_ss_gpio_state_t *const state)
Read the current value of a single pin on a given SS GPIO port.
uint32_t gpio_inten
Interrupt Enable.
int qm_ss_gpio_restore_context(const qm_ss_gpio_t gpio, const qm_ss_gpio_context_t *const ctx)
Restore SS GPIO context.
void(* callback)(void *data, uint32_t int_status)
User callback.
uint32_t gpio_swporta_dr
Port A Data.
uint32_t direction
SS GPIO direction, 0b: input, 1b: output.
uint32_t int_debounce
Debounce on/off.
void * callback_data
Callback user data.
uint32_t gpio_ls_sync
Synchronization Level.