Intel® Quark™ Microcontroller Software Interface  1.4.0
Intel® Quark™ Microcontroller BSP
SoC Registers (D2000)

Quark D2000 SoC Registers. More...

Data Structures

struct  qm_scss_ccu_reg_t
 System Core register map. More...
 
struct  qm_scss_gp_reg_t
 General Purpose register map. More...
 
struct  qm_scss_cmp_reg_t
 Comparator register map. More...
 
struct  qm_scss_pmu_reg_t
 Power Management register map. More...
 
struct  qm_aonc_reg_t
 Always-on Counter Controller register map. More...
 
struct  qm_scss_peripheral_reg_t
 Peripheral Registers register map. More...
 
struct  qm_scss_pmux_reg_t
 Pin MUX register map. More...
 
struct  qm_scss_info_reg_t
 Information register map. More...
 
struct  qm_pwm_channel_t
 PWM / Timer channel register map. More...
 
struct  qm_pwm_reg_t
 PWM / Timer register map. More...
 
struct  qm_wdt_reg_t
 Watchdog timer register map. More...
 
struct  qm_uart_reg_t
 UART register map. More...
 
struct  qm_spi_reg_t
 SPI register map. More...
 
struct  qm_rtc_reg_t
 RTC register map. More...
 
struct  qm_i2c_reg_t
 I2C register map. More...
 
struct  qm_gpio_reg_t
 GPIO register map. More...
 
struct  qm_adc_reg_t
 ADC register map. More...
 
struct  qm_flash_reg_t
 Flash register map. More...
 
struct  qm_mpr_reg_t
 Memory Protection Region register map. More...
 
struct  pic_timer_reg_pad_t
 PIC timer register structure. More...
 
struct  qm_pic_timer_reg_t
 PIC timer register map. More...
 
struct  mvic_reg_pad_t
 MVIC register structure. More...
 
struct  qm_mvic_reg_t
 MVIC register map. More...
 
struct  qm_dma_chan_reg_t
 DMA channel register map. More...
 
struct  qm_dma_int_reg_t
 DMA interrupt register map. More...
 
struct  qm_dma_misc_reg_t
 DMA miscellaneous register map. More...
 

System Core

qm_scss_ccu_reg_t test_scss_ccu
 

General Purpose

qm_scss_gp_reg_t test_scss_gp
 

Comparator

qm_scss_cmp_reg_t test_scss_cmp
 

Power Management

qm_scss_pmu_reg_t test_scss_pmu
 

Always-on Counters.

enum  qm_aonc_t
 Number of Always-on counter controllers. More...
 
qm_aonc_reg_t test_aonc_instance [QM_AONC_NUM]
 
qm_aonc_reg_ttest_aonc [QM_AONC_NUM]
 
qm_aonc_reg_tqm_aonc [QM_AONC_NUM]
 

Peripheral Registers

qm_scss_peripheral_reg_t test_scss_peripheral
 

Pin MUX

qm_scss_pmux_reg_t test_scss_pmux
 

ID

qm_scss_info_reg_t test_scss_info
 

PWM / Timer

enum  qm_pwm_t
 Number of PWM / Timer controllers. More...
 
enum  qm_pwm_id_t
 PWM ID type. More...
 
qm_pwm_reg_t test_pwm_instance [QM_PWM_NUM]
 
qm_pwm_reg_ttest_pwm [QM_PWM_NUM]
 
qm_pwm_reg_tqm_pwm [QM_PWM_NUM]
 

WDT

enum  qm_wdt_t
 Number of WDT controllers. More...
 
qm_wdt_reg_t test_wdt_instance [QM_WDT_NUM]
 
qm_wdt_reg_ttest_wdt [QM_WDT_NUM]
 
qm_wdt_reg_tqm_wdt [QM_WDT_NUM]
 

UART

WDT timeout table (in clock cycles): Each table entry corresponds with the value loaded into the WDT at the time of a WDT reload for the corresponding timeout range register value.

TORR | Timeout (Clock Cycles) 0. | 2^16 (65536)

  1. | 2^17 (131072)
  2. | 2^18 (262144)
  3. | 2^19 (524288)
  4. | 2^20 (1048576)
  5. | 2^21 (2097152)
  6. | 2^22 (4194304)
  7. | 2^23 (8388608)
  8. | 2^24 (16777216)
  9. | 2^25 (33554432)
  10. | 2^26 (67108864)
  11. | 2^27 (134217728)
  12. | 2^28 (268435456)
  13. | 2^29 (536870912)
  14. | 2^30 (1073741824)
  15. | 2^31 (2147483648)
enum  qm_uart_t
 Number of UART controllers. More...
 
qm_uart_reg_t test_uart_instance
 
qm_uart_reg_ttest_uart [QM_UART_NUM]
 
qm_uart_reg_tqm_uart [QM_UART_NUM]
 

SPI

enum  qm_spi_t
 Number of SPI controllers. More...
 
qm_spi_reg_t test_spi
 
qm_spi_reg_ttest_spi_controllers [QM_SPI_NUM]
 
qm_spi_reg_tqm_spi_controllers [QM_SPI_NUM]
 Extern qm_spi_reg_t* array declared at qm_soc_regs.h .
 

RTC

enum  qm_rtc_t
 Number of RTC controllers. More...
 
qm_rtc_reg_t test_rtc_instance [QM_RTC_NUM]
 
qm_rtc_reg_ttest_rtc [QM_RTC_NUM]
 
qm_rtc_reg_tqm_rtc [QM_RTC_NUM]
 

I2C

enum  qm_i2c_t
 Number of I2C controllers. More...
 
qm_i2c_reg_t test_i2c_instance [QM_I2C_NUM]
 
qm_i2c_reg_ttest_i2c [QM_I2C_NUM]
 
qm_i2c_reg_tqm_i2c [QM_I2C_NUM]
 I2C register block. More...
 

GPIO

enum  qm_gpio_t
 Number of GPIO controllers. More...
 
qm_gpio_reg_t test_gpio_instance
 
qm_gpio_reg_ttest_gpio [QM_GPIO_NUM]
 
qm_gpio_reg_tqm_gpio [QM_GPIO_NUM]
 

ADC

enum  qm_adc_t
 Number of ADC controllers. More...
 
qm_adc_reg_t test_adc
 

Flash

enum  qm_flash_t
 Number of Flash controllers. More...
 
qm_flash_reg_t test_flash_instance
 
qm_flash_reg_ttest_flash [QM_FLASH_NUM]
 
uint8_t test_flash_page [0x800]
 
qm_flash_reg_tqm_flash [QM_FLASH_NUM]
 

Flash Protection Region

enum  qm_fpr_id_t {
  QM_FPR_0, QM_FPR_1, QM_FPR_2, QM_FPR_3 ,
  QM_FPR_0, QM_FPR_1, QM_FPR_2, QM_FPR_3
}
 FPR register map. More...
 

Memory Protection Region

enum  qm_mpr_id_t {
  QM_MPR_0 = 0, QM_MPR_1, QM_MPR_2, QM_MPR_3,
  QM_MPR_NUM, QM_MPR_0 = 0, QM_MPR_1, QM_MPR_2,
  QM_MPR_3, QM_MPR_NUM
}
 
qm_mpr_reg_t test_mpr
 

PIC

qm_pic_timer_reg_t test_pic_timer
 

Peripheral Clock

enum  clk_periph_t {
  CLK_PERIPH_REGISTER = BIT(0), CLK_PERIPH_CLK = BIT(1), CLK_PERIPH_I2C_M0 = BIT(2), CLK_PERIPH_SPI_S = BIT(4),
  CLK_PERIPH_SPI_M0 = BIT(5), CLK_PERIPH_GPIO_INTERRUPT = BIT(7), CLK_PERIPH_GPIO_DB = BIT(8), CLK_PERIPH_WDT_REGISTER = BIT(10),
  CLK_PERIPH_RTC_REGISTER = BIT(11), CLK_PERIPH_PWM_REGISTER = BIT(12), CLK_PERIPH_GPIO_REGISTER = BIT(13), CLK_PERIPH_SPI_M0_REGISTER,
  CLK_PERIPH_SPI_S_REGISTER, CLK_PERIPH_UARTA_REGISTER = BIT(17), CLK_PERIPH_UARTB_REGISTER = BIT(18), CLK_PERIPH_I2C_M0_REGISTER,
  CLK_PERIPH_ADC = BIT(22), CLK_PERIPH_ADC_REGISTER = BIT(23), CLK_PERIPH_ALL = 0xCFFFFF, CLK_PERIPH_REGISTER = BIT(0),
  CLK_PERIPH_CLK = BIT(1), CLK_PERIPH_I2C_M0 = BIT(2), CLK_PERIPH_I2C_M1 = BIT(3), CLK_PERIPH_SPI_S = BIT(4),
  CLK_PERIPH_SPI_M0 = BIT(5), CLK_PERIPH_SPI_M1 = BIT(6), CLK_PERIPH_GPIO_INTERRUPT = BIT(7), CLK_PERIPH_GPIO_DB = BIT(8),
  CLK_PERIPH_I2S = BIT(9), CLK_PERIPH_WDT_REGISTER = BIT(10), CLK_PERIPH_RTC_REGISTER = BIT(11), CLK_PERIPH_PWM_REGISTER = BIT(12),
  CLK_PERIPH_GPIO_REGISTER = BIT(13), CLK_PERIPH_SPI_M0_REGISTER, CLK_PERIPH_SPI_M1_REGISTER, CLK_PERIPH_SPI_S_REGISTER,
  CLK_PERIPH_UARTA_REGISTER = BIT(17), CLK_PERIPH_UARTB_REGISTER = BIT(18), CLK_PERIPH_I2C_M0_REGISTER, CLK_PERIPH_I2C_M1_REGISTER,
  CLK_PERIPH_I2S_REGISTER = BIT(21), CLK_PERIPH_ALL = 0x3FFFFF
}
 Peripheral clock register map. More...
 

MVIC

qm_mvic_reg_t test_mvic
 
qm_ioapic_reg_t test_ioapic
 

DMA

enum  qm_dma_t { QM_DMA_0, QM_DMA_NUM, QM_DMA_0, QM_DMA_NUM }
 DMA instances. More...
 
enum  qm_dma_channel_id_t {
  QM_DMA_CHANNEL_0 = 0, QM_DMA_CHANNEL_1, QM_DMA_CHANNEL_NUM, QM_DMA_CHANNEL_0 = 0,
  QM_DMA_CHANNEL_1, QM_DMA_CHANNEL_2, QM_DMA_CHANNEL_3, QM_DMA_CHANNEL_4,
  QM_DMA_CHANNEL_5, QM_DMA_CHANNEL_6, QM_DMA_CHANNEL_7, QM_DMA_CHANNEL_NUM
}
 DMA channel IDs. More...
 
enum  qm_dma_handshake_interface_t {
  DMA_HW_IF_UART_A_TX = 0x0, DMA_HW_IF_UART_A_RX = 0x1, DMA_HW_IF_UART_B_TX = 0x2, DMA_HW_IF_UART_B_RX = 0x3,
  DMA_HW_IF_SPI_MASTER_0_TX = 0x4, DMA_HW_IF_SPI_MASTER_0_RX = 0x5, DMA_HW_IF_SPI_SLAVE_TX = 0x8, DMA_HW_IF_SPI_SLAVE_RX = 0x9,
  DMA_HW_IF_I2C_MASTER_0_TX = 0xc, DMA_HW_IF_I2C_MASTER_0_RX = 0xd, DMA_HW_IF_UART_A_TX = 0x0, DMA_HW_IF_UART_A_RX = 0x1,
  DMA_HW_IF_UART_B_TX = 0x2, DMA_HW_IF_UART_B_RX = 0x3, DMA_HW_IF_SPI_MASTER_0_TX = 0x4, DMA_HW_IF_SPI_MASTER_0_RX = 0x5,
  DMA_HW_IF_SPI_MASTER_1_TX = 0x6, DMA_HW_IF_SPI_MASTER_1_RX = 0x7, DMA_HW_IF_SPI_SLAVE_TX = 0x8, DMA_HW_IF_SPI_SLAVE_RX = 0x9,
  DMA_HW_IF_I2S_PLAYBACK = 0xa, DMA_HW_IF_I2S_CAPTURE = 0xb, DMA_HW_IF_I2C_MASTER_0_TX = 0xc, DMA_HW_IF_I2C_MASTER_0_RX = 0xd,
  DMA_HW_IF_I2C_MASTER_1_TX = 0xe, DMA_HW_IF_I2C_MASTER_1_RX = 0xf
}
 DMA hardware handshake interfaces. More...
 
qm_dma_reg_t test_dma_instance [QM_DMA_NUM]
 
qm_dma_reg_t * test_dma [QM_DMA_NUM]
 
qm_dma_reg_t * qm_dma [QM_DMA_NUM]
 

Versioning

uint32_t test_rom_version
 

Detailed Description

Quark D2000 SoC Registers.

Enumeration Type Documentation

Peripheral clock register map.

Enumerator
CLK_PERIPH_REGISTER 

Peripheral Clock Gate Enable.

CLK_PERIPH_CLK 

Peripheral Clock Enable.

CLK_PERIPH_I2C_M0 

I2C Master 0 Clock Enable.

CLK_PERIPH_SPI_S 

SPI Slave Clock Enable.

CLK_PERIPH_SPI_M0 

SPI Master 0 Clock Enable.

CLK_PERIPH_GPIO_INTERRUPT 

GPIO Interrupt Clock Enable.

CLK_PERIPH_GPIO_DB 

GPIO Debounce Clock Enable.

CLK_PERIPH_WDT_REGISTER 

Watchdog Clock Enable.

CLK_PERIPH_RTC_REGISTER 

RTC Clock Gate Enable.

CLK_PERIPH_PWM_REGISTER 

PWM Clock Gate Enable.

CLK_PERIPH_GPIO_REGISTER 

GPIO Clock Gate Enable.

CLK_PERIPH_SPI_M0_REGISTER 

SPI Master 0 Clock Gate Enable.

CLK_PERIPH_SPI_S_REGISTER 

SPI Slave Clock Gate Enable.

CLK_PERIPH_UARTA_REGISTER 

UARTA Clock Gate Enable.

CLK_PERIPH_UARTB_REGISTER 

UARTB Clock Gate Enable.

CLK_PERIPH_I2C_M0_REGISTER 

I2C Master 0 Clock Gate Enable.

CLK_PERIPH_ADC 

ADC Clock Enable.

CLK_PERIPH_ADC_REGISTER 

ADC Clock Gate Enable.

CLK_PERIPH_ALL 

Quark D2000 peripherals Enable.

CLK_PERIPH_REGISTER 

Peripheral Clock Gate Enable.

CLK_PERIPH_CLK 

Peripheral Clock Enable.

CLK_PERIPH_I2C_M0 

I2C Master 0 Clock Enable.

CLK_PERIPH_I2C_M1 

I2C Master 1 Clock Enable.

CLK_PERIPH_SPI_S 

SPI Slave Clock Enable.

CLK_PERIPH_SPI_M0 

SPI Master 0 Clock Enable.

CLK_PERIPH_SPI_M1 

SPI Master 1 Clock Enable.

CLK_PERIPH_GPIO_INTERRUPT 

GPIO Interrupt Clock Enable.

CLK_PERIPH_GPIO_DB 

GPIO Debounce Clock Enable.

CLK_PERIPH_I2S 

I2S Clock Enable.

CLK_PERIPH_WDT_REGISTER 

Watchdog Clock Enable.

CLK_PERIPH_RTC_REGISTER 

RTC Clock Gate Enable.

CLK_PERIPH_PWM_REGISTER 

PWM Clock Gate Enable.

CLK_PERIPH_GPIO_REGISTER 

GPIO Clock Gate Enable.

CLK_PERIPH_SPI_M0_REGISTER 

SPI Master 0 Clock Gate Enable.

CLK_PERIPH_SPI_M1_REGISTER 

SPI Master 1 Clock Gate Enable.

CLK_PERIPH_SPI_S_REGISTER 

SPI Slave Clock Gate Enable.

CLK_PERIPH_UARTA_REGISTER 

UARTA Clock Gate Enable.

CLK_PERIPH_UARTB_REGISTER 

UARTB Clock Gate Enable.

CLK_PERIPH_I2C_M0_REGISTER 

I2C Master 0 Clock Gate Enable.

CLK_PERIPH_I2C_M1_REGISTER 

I2C Master 1 Clock Gate Enable.

CLK_PERIPH_I2S_REGISTER 

I2S Clock Gate Enable.

CLK_PERIPH_ALL 

Quark SE peripherals Mask.

Definition at line 1368 of file qm_soc_regs.h.

enum qm_adc_t

Number of ADC controllers.

Definition at line 1066 of file qm_soc_regs.h.

enum qm_aonc_t

Number of Always-on counter controllers.

Definition at line 255 of file qm_soc_regs.h.

DMA channel IDs.

Enumerator
QM_DMA_CHANNEL_0 

DMA channel id for channel 0.

QM_DMA_CHANNEL_1 

DMA channel id for channel 1.

QM_DMA_CHANNEL_NUM 

Number of DMA channels.

QM_DMA_CHANNEL_0 

DMA channel id for channel 0.

QM_DMA_CHANNEL_1 

DMA channel id for channel 1.

QM_DMA_CHANNEL_2 

DMA channel id for channel 2.

QM_DMA_CHANNEL_3 

DMA channel id for channel 3.

QM_DMA_CHANNEL_4 

DMA channel id for channel 4.

QM_DMA_CHANNEL_5 

DMA channel id for channel 5.

QM_DMA_CHANNEL_6 

DMA channel id for channel 6.

QM_DMA_CHANNEL_7 

DMA channel id for channel 7.

QM_DMA_CHANNEL_NUM 

Number of DMA channels.

Definition at line 1486 of file qm_soc_regs.h.

DMA hardware handshake interfaces.

Enumerator
DMA_HW_IF_UART_A_TX 

UART_A_TX.

DMA_HW_IF_UART_A_RX 

UART_A_RX.

DMA_HW_IF_UART_B_TX 

UART_B_TX.

DMA_HW_IF_UART_B_RX 

UART_B_RX.

DMA_HW_IF_SPI_MASTER_0_TX 

SPI_Master_0_TX.

DMA_HW_IF_SPI_MASTER_0_RX 

SPI_Master_0_RX.

DMA_HW_IF_SPI_SLAVE_TX 

SPI_Slave_TX.

DMA_HW_IF_SPI_SLAVE_RX 

SPI_Slave_RX.

DMA_HW_IF_I2C_MASTER_0_TX 

I2C_Master_0_TX.

DMA_HW_IF_I2C_MASTER_0_RX 

I2C_Master_0_RX.

DMA_HW_IF_UART_A_TX 

UART_A_TX.

DMA_HW_IF_UART_A_RX 

UART_A_RX.

DMA_HW_IF_UART_B_TX 

UART_B_TX.

DMA_HW_IF_UART_B_RX 

UART_B_RX.

DMA_HW_IF_SPI_MASTER_0_TX 

SPI_Master_0_TX.

DMA_HW_IF_SPI_MASTER_0_RX 

SPI_Master_0_RX.

DMA_HW_IF_SPI_MASTER_1_TX 

SPI_Master_1_TX.

DMA_HW_IF_SPI_MASTER_1_RX 

SPI_Master_1_RX.

DMA_HW_IF_SPI_SLAVE_TX 

SPI_Slave_TX.

DMA_HW_IF_SPI_SLAVE_RX 

SPI_Slave_RX.

DMA_HW_IF_I2S_PLAYBACK 

I2S_Playback channel.

DMA_HW_IF_I2S_CAPTURE 

I2S_Capture channel.

DMA_HW_IF_I2C_MASTER_0_TX 

I2C_Master_0_TX.

DMA_HW_IF_I2C_MASTER_0_RX 

I2C_Master_0_RX.

DMA_HW_IF_I2C_MASTER_1_TX 

I2C_Master_1_TX.

DMA_HW_IF_I2C_MASTER_1_RX 

I2C_Master_1_RX.

Definition at line 1493 of file qm_soc_regs.h.

enum qm_dma_t

DMA instances.

Enumerator
QM_DMA_0 

DMA controller id.

QM_DMA_NUM 

Number of DMA controllers.

QM_DMA_0 

DMA controller id.

QM_DMA_NUM 

Number of DMA controllers.

Definition at line 1480 of file qm_soc_regs.h.

enum qm_flash_t

Number of Flash controllers.

Definition at line 1141 of file qm_soc_regs.h.

FPR register map.

Enumerator
QM_FPR_0 

FPR 0.

QM_FPR_1 

FPR 1.

QM_FPR_2 

FPR 2.

QM_FPR_3 

FPR 3.

QM_FPR_0 

FPR 0.

QM_FPR_1 

FPR 1.

QM_FPR_2 

FPR 2.

QM_FPR_3 

FPR 3.

Definition at line 1265 of file qm_soc_regs.h.

enum qm_gpio_t

Number of GPIO controllers.

Definition at line 1014 of file qm_soc_regs.h.

enum qm_i2c_t

Number of I2C controllers.

Definition at line 861 of file qm_soc_regs.h.

Enumerator
QM_MPR_0 

Memory Protection Region 0.

QM_MPR_1 

Memory Protection Region 1.

QM_MPR_2 

Memory Protection Region 2.

QM_MPR_3 

Memory Protection Region 3.

QM_MPR_NUM 

Number of Memory Protection Regions.

QM_MPR_0 

Memory Protection Region 0.

QM_MPR_1 

Memory Protection Region 1.

QM_MPR_2 

Memory Protection Region 2.

QM_MPR_3 

Memory Protection Region 3.

QM_MPR_NUM 

Number of Memory Protection Regions.

Definition at line 1286 of file qm_soc_regs.h.

PWM ID type.

Definition at line 386 of file qm_soc_regs.h.

enum qm_pwm_t

Number of PWM / Timer controllers.

Definition at line 383 of file qm_soc_regs.h.

enum qm_rtc_t

Number of RTC controllers.

Definition at line 818 of file qm_soc_regs.h.

enum qm_spi_t

Number of SPI controllers.

Definition at line 709 of file qm_soc_regs.h.

enum qm_uart_t

Number of UART controllers.

Definition at line 655 of file qm_soc_regs.h.

enum qm_wdt_t

Number of WDT controllers.

Definition at line 467 of file qm_soc_regs.h.

Variable Documentation

qm_i2c_reg_t* qm_i2c[QM_I2C_NUM]

I2C register block.

Definition at line 20 of file qm_i2c.c.