5 #ifndef __POWER_STATES_H__
6 #define __POWER_STATES_H__
9 #include "qm_soc_regs.h"
63 #if (ENABLE_RESTORE_CONTEXT) && (!QM_SENSOR)
188 #if (ENABLE_RESTORE_CONTEXT) && (!QM_SENSOR) && (!UNIT_TEST)
196 #define qm_x86_set_resume_vector(_restore_label, shared_mem) \
197 __asm__ __volatile__("movl $" #_restore_label ", %[trap]\n\t" \
200 [trap] "m"(shared_mem) \
212 #define qm_x86_save_context(stack_pointer) \
213 __asm__ __volatile__("sub $8, %%esp\n\t" \
215 "lea %[stackpointer], %%eax\n\t" \
218 "movl %%dr0, %%edx\n\t" \
220 "movl %%dr1, %%edx\n\t" \
222 "movl %%dr2, %%edx\n\t" \
224 "movl %%dr3, %%edx\n\t" \
226 "movl %%dr6, %%edx\n\t" \
228 "movl %%dr7, %%edx\n\t" \
230 "movl %%esp, (%%eax)\n\t" \
233 [stackpointer] "m"(stack_pointer) \
243 #define qm_x86_restore_context(_restore_label, stack_pointer) \
244 __asm__ __volatile__(#_restore_label ":\n\t" \
245 "lea %[stackpointer], %%eax\n\t" \
246 "movl (%%eax), %%esp\n\t" \
248 "movl %%edx, %%dr7\n\t" \
250 "movl %%edx, %%dr6\n\t" \
252 "movl %%edx, %%dr3\n\t" \
254 "movl %%edx, %%dr2\n\t" \
256 "movl %%edx, %%dr1\n\t" \
258 "movl %%edx, %%dr0\n\t" \
262 "add $8, %%esp\n\t" \
265 [stackpointer] "m"(stack_pointer) \
270 #define qm_x86_set_resume_vector(_restore_label, shared_mem)
271 #define qm_x86_save_context(stack_pointer)
272 #define qm_x86_restore_context(_restore_label, stack_pointer)
void qm_power_cpu_c1(void)
Enter Host C1 state.
void qm_power_soc_deep_sleep(const qm_power_wake_event_t wake_event)
Put SoC to deep sleep.
void qm_power_cpu_c2lp(void)
Enter Host C2LP state or SoC LPSS state.
void qm_power_soc_deep_sleep_restore(void)
Enter SoC deep sleep state and restore after wake up.
void qm_power_soc_sleep()
Put SoC to sleep.
void qm_power_soc_sleep_restore(void)
Enter SoC sleep state and restore after wake up.
void qm_power_soc_set_x86_restore_flag(void)
Enable the x86 startup restore flag, see GPS0 #define in qm_soc_regs.h.
void qm_power_sleep_wait(void)
Save context, enter x86 C2 power save state and restore after wake up.
void qm_power_cpu_c2(void)
Enter Host C2 state or SoC LPSS state.