13 #define I2C_POLL_COUNT (1000000)
14 #define I2C_POLL_MICROSECOND (1)
16 static uint32_t i2c_base[QM_SS_I2C_NUM] = {QM_SS_I2C_0_BASE, QM_SS_I2C_1_BASE};
18 static volatile uint32_t i2c_write_pos[QM_SS_I2C_NUM],
19 i2c_read_pos[QM_SS_I2C_NUM], i2c_read_cmd_send[QM_SS_I2C_NUM];
21 static void controller_enable(
const qm_ss_i2c_t i2c);
22 static int controller_disable(
const qm_ss_i2c_t i2c);
29 uint32_t data_cmd = 0, count_tx = (QM_SS_I2C_FIFO_SIZE - TX_TL);
30 uint32_t write_buffer_remaining = transfer->
tx_len - i2c_write_pos[i2c];
31 uint32_t read_buffer_remaining = transfer->
rx_len - i2c_read_pos[i2c];
33 while ((count_tx) && write_buffer_remaining) {
35 write_buffer_remaining--;
39 data_cmd = QM_SS_I2C_DATA_CMD_PUSH |
40 i2c_transfer[i2c]->
tx[i2c_write_pos[i2c]];
45 if (i2c_transfer[i2c]->stop && (read_buffer_remaining == 0) &&
46 (write_buffer_remaining == 0)) {
48 data_cmd |= QM_SS_I2C_DATA_CMD_STOP;
52 QM_SS_I2C_WRITE_DATA_CMD(controller, data_cmd);
60 return write_buffer_remaining;
63 static void handle_i2c_error_interrupt(
const qm_ss_i2c_t i2c)
65 uint32_t controller = i2c_base[i2c];
70 if (QM_SS_I2C_READ_INTR_STAT(controller) &
71 QM_SS_I2C_INTR_STAT_TX_OVER) {
76 QM_SS_I2C_CLEAR_TX_OVER_INTR(controller);
80 if (QM_SS_I2C_READ_INTR_STAT(controller) &
81 QM_SS_I2C_INTR_STAT_RX_UNDER) {
86 QM_SS_I2C_CLEAR_RX_UNDER_INTR(controller);
90 if (QM_SS_I2C_READ_INTR_STAT(controller) &
91 QM_SS_I2C_INTR_STAT_RX_OVER) {
96 QM_SS_I2C_CLEAR_RX_OVER_INTR(controller);
100 if ((QM_SS_I2C_READ_INTR_STAT(controller) &
101 QM_SS_I2C_INTR_STAT_TX_ABRT)) {
103 QM_ASSERT(!(QM_SS_I2C_READ_TX_ABRT_SOURCE(controller) &
104 QM_SS_I2C_TX_ABRT_SBYTE_NORSTRT));
108 status |= (QM_SS_I2C_READ_TX_ABRT_SOURCE(controller) &
109 QM_SS_I2C_TX_ABRT_SOURCE_ALL_MASK);
112 QM_SS_I2C_CLEAR_TX_ABRT_INTR(controller);
118 QM_SS_I2C_MASK_ALL_INTERRUPTS(controller);
120 controller_disable(i2c);
121 if (i2c_transfer[i2c]->callback) {
122 i2c_transfer[i2c]->
callback(i2c_transfer[i2c]->callback_data,
127 static void handle_i2c_rx_avail_interrupt(
const qm_ss_i2c_t i2c)
130 uint32_t controller = i2c_base[i2c];
131 uint32_t read_buffer_remaining = transfer->
rx_len - i2c_read_pos[i2c];
134 if ((QM_SS_I2C_READ_INTR_STAT(controller) &
135 QM_SS_I2C_INTR_STAT_RX_FULL)) {
137 while (read_buffer_remaining &&
138 (QM_SS_I2C_READ_RXFLR(controller))) {
139 QM_SS_I2C_READ_RX_FIFO(controller);
141 i2c_transfer[i2c]->
rx[i2c_read_pos[i2c]] =
142 QM_SS_I2C_READ_DATA_CMD(controller);
143 read_buffer_remaining--;
146 if (read_buffer_remaining == 0) {
150 QM_SS_I2C_MASK_INTERRUPT(
152 QM_SS_I2C_INTR_MASK_RX_FULL |
153 QM_SS_I2C_INTR_MASK_TX_EMPTY);
155 if (i2c_transfer[i2c]->stop) {
156 controller_disable(i2c);
159 if (i2c_transfer[i2c]->callback) {
161 i2c_transfer[i2c]->callback_data, 0,
166 if (read_buffer_remaining > 0 &&
167 read_buffer_remaining < (RX_TL + 1)) {
172 QM_SS_I2C_CLEAR_RX_TL(controller);
173 QM_SS_I2C_WRITE_RX_TL(controller,
174 (read_buffer_remaining - 1));
183 static void handle_i2c_tx_req_interrupt(
const qm_ss_i2c_t i2c)
186 uint32_t controller = i2c_base[i2c];
188 uint32_t read_buffer_remaining = transfer->
rx_len - i2c_read_pos[i2c];
189 uint32_t write_buffer_remaining = transfer->
tx_len - i2c_write_pos[i2c];
190 uint32_t missing_bytes;
192 if ((QM_SS_I2C_READ_INTR_STAT(controller) &
193 QM_SS_I2C_INTR_STAT_TX_EMPTY)) {
195 if ((QM_SS_I2C_READ_STATUS(controller) &
196 QM_SS_I2C_STATUS_TFE) &&
197 (i2c_transfer[i2c]->tx != NULL) &&
198 (write_buffer_remaining == 0) &&
199 (read_buffer_remaining == 0)) {
201 QM_SS_I2C_MASK_INTERRUPT(controller,
202 QM_SS_I2C_INTR_MASK_TX_EMPTY);
207 if (i2c_transfer[i2c]->stop) {
208 controller_disable(i2c);
212 if (i2c_transfer[i2c]->callback) {
214 i2c_transfer[i2c]->callback_data, 0,
219 write_buffer_remaining =
220 i2c_fill_tx_fifo(i2c, i2c_transfer[i2c], controller);
227 missing_bytes = read_buffer_remaining - i2c_read_cmd_send[i2c];
231 QM_ASSERT(QM_SS_I2C_READ_RXFLR(controller) <= missing_bytes);
235 QM_SS_I2C_FIFO_SIZE - QM_SS_I2C_READ_TXFLR(controller);
237 if (count_tx > missing_bytes) {
238 count_tx -= missing_bytes;
243 while (i2c_read_cmd_send[i2c] &&
244 (write_buffer_remaining == 0) && count_tx) {
246 i2c_read_cmd_send[i2c]--;
252 if (i2c_transfer[i2c]->stop &&
253 (i2c_read_cmd_send[i2c] == 0)) {
255 QM_SS_I2C_WRITE_DATA_CMD(
256 controller, (QM_SS_I2C_DATA_CMD_CMD |
257 QM_SS_I2C_DATA_CMD_PUSH |
258 QM_SS_I2C_DATA_CMD_STOP));
262 QM_SS_I2C_WRITE_DATA_CMD(
263 controller, (QM_SS_I2C_DATA_CMD_CMD |
264 QM_SS_I2C_DATA_CMD_PUSH));
270 if ((write_buffer_remaining == 0) &&
271 (read_buffer_remaining == 0)) {
272 QM_SS_I2C_CLEAR_TX_TL(controller);
277 static void handle_i2c_stop_det_interrupt(
const qm_ss_i2c_t i2c)
279 uint32_t controller = i2c_base[i2c];
281 if ((QM_SS_I2C_READ_INTR_STAT(controller) & QM_SS_I2C_INTR_STAT_STOP)) {
284 QM_SS_I2C_CLEAR_STOP_DET_INTR(controller);
286 if (i2c_transfer[i2c]->callback) {
296 handle_i2c_error_interrupt(QM_SS_I2C_0);
301 handle_i2c_rx_avail_interrupt(QM_SS_I2C_0);
306 handle_i2c_tx_req_interrupt(QM_SS_I2C_0);
311 handle_i2c_stop_det_interrupt(QM_SS_I2C_0);
316 handle_i2c_error_interrupt(QM_SS_I2C_1);
321 handle_i2c_rx_avail_interrupt(QM_SS_I2C_1);
326 handle_i2c_tx_req_interrupt(QM_SS_I2C_1);
331 handle_i2c_stop_det_interrupt(QM_SS_I2C_1);
334 static uint32_t get_lo_cnt(uint32_t lo_time_ns)
339 static uint32_t get_hi_cnt(
qm_ss_i2c_t i2c, uint32_t hi_time_ns)
341 uint32_t controller = i2c_base[i2c];
344 (QM_SS_I2C_READ_SPKLEN(controller)));
350 QM_CHECK(i2c < QM_SS_I2C_NUM, -EINVAL);
351 QM_CHECK(cfg != NULL, -EINVAL);
353 uint32_t controller = i2c_base[i2c], lcnt = 0, hcnt = 0, min_lcnt = 0,
356 QM_SS_I2C_WRITE_CLKEN(controller);
359 QM_SS_I2C_MASK_ALL_INTERRUPTS(controller);
362 if (controller_disable(i2c)) {
367 QM_SS_I2C_WRITE_RESTART_EN(controller);
368 QM_SS_I2C_WRITE_ADDRESS_MODE(controller, cfg->
address_mode);
378 QM_SS_I2C_CLEAR_SPKLEN(controller);
379 QM_SS_I2C_CLEAR_SPEED(controller);
381 switch (cfg->
speed) {
384 QM_SS_I2C_WRITE_SPEED(controller, QM_SS_I2C_CON_SPEED_SS);
385 QM_SS_I2C_WRITE_SPKLEN(controller, QM_SS_I2C_SPK_LEN_SS);
387 min_lcnt = get_lo_cnt(QM_I2C_MIN_SS_NS);
388 lcnt = get_lo_cnt(QM_I2C_SS_50_DC_NS);
389 hcnt = get_hi_cnt(i2c, QM_I2C_SS_50_DC_NS);
394 QM_SS_I2C_WRITE_SPEED(controller, QM_SS_I2C_CON_SPEED_FS);
395 QM_SS_I2C_WRITE_SPKLEN(controller, QM_SS_I2C_SPK_LEN_FS);
397 min_lcnt = get_lo_cnt(QM_I2C_MIN_FS_NS);
398 lcnt = get_lo_cnt(QM_I2C_FS_50_DC_NS);
399 hcnt = get_hi_cnt(i2c, QM_I2C_FS_50_DC_NS);
402 #if HAS_SS_I2C_FAST_PLUS_SPEED
405 QM_SS_I2C_WRITE_SPEED(controller, QM_SS_I2C_CON_SPEED_FSP);
406 QM_SS_I2C_WRITE_SPKLEN(controller, QM_SS_I2C_SPK_LEN_FSP);
408 min_lcnt = get_lo_cnt(QM_I2C_MIN_FSP_NS);
409 lcnt = get_lo_cnt(QM_I2C_FSP_50_DC_NS);
410 hcnt = get_hi_cnt(i2c, QM_I2C_FSP_50_DC_NS);
416 if (hcnt > QM_SS_I2C_IC_HCNT_MAX || hcnt < QM_SS_I2C_IC_HCNT_MIN) {
420 if (lcnt > QM_SS_I2C_IC_LCNT_MAX || lcnt < QM_SS_I2C_IC_LCNT_MIN) {
426 if (lcnt < min_lcnt) {
427 lcnt_diff = (min_lcnt - lcnt);
433 QM_SS_I2C_CLEAR_SS_SCL_HCNT(controller);
434 QM_SS_I2C_CLEAR_SS_SCL_LCNT(controller);
436 QM_SS_I2C_WRITE_SS_SCL_HCNT(controller, hcnt);
437 QM_SS_I2C_WRITE_SS_SCL_LCNT(controller, lcnt);
440 QM_SS_I2C_CLEAR_FS_SCL_HCNT(controller);
441 QM_SS_I2C_CLEAR_FS_SCL_LCNT(controller);
443 QM_SS_I2C_WRITE_FS_SCL_HCNT(controller, hcnt);
444 QM_SS_I2C_WRITE_FS_SCL_LCNT(controller, lcnt);
451 const uint16_t lo_cnt,
const uint16_t hi_cnt)
453 QM_CHECK(i2c < QM_SS_I2C_NUM, -EINVAL);
454 QM_CHECK(hi_cnt < QM_SS_I2C_IC_HCNT_MAX &&
455 hi_cnt > QM_SS_I2C_IC_HCNT_MIN,
457 QM_CHECK(lo_cnt < QM_SS_I2C_IC_LCNT_MAX &&
458 lo_cnt > QM_SS_I2C_IC_LCNT_MIN,
461 uint32_t controller = i2c_base[i2c];
463 QM_SS_I2C_CLEAR_SPKLEN(controller);
464 QM_SS_I2C_CLEAR_SPEED(controller);
468 QM_SS_I2C_WRITE_SPKLEN(controller, QM_SS_I2C_SPK_LEN_SS);
469 QM_SS_I2C_WRITE_SPEED(controller, QM_SS_I2C_CON_SPEED_SS);
471 QM_SS_I2C_CLEAR_SS_SCL_HCNT(controller);
472 QM_SS_I2C_CLEAR_SS_SCL_LCNT(controller);
474 QM_SS_I2C_WRITE_SS_SCL_HCNT(controller, hi_cnt);
475 QM_SS_I2C_WRITE_SS_SCL_LCNT(controller, lo_cnt);
479 QM_SS_I2C_WRITE_SPKLEN(controller, QM_SS_I2C_SPK_LEN_FS);
480 QM_SS_I2C_WRITE_SPEED(controller, QM_SS_I2C_CON_SPEED_FS);
482 QM_SS_I2C_CLEAR_FS_SCL_HCNT(controller);
483 QM_SS_I2C_CLEAR_FS_SCL_LCNT(controller);
485 QM_SS_I2C_WRITE_FS_SCL_HCNT(controller, hi_cnt);
486 QM_SS_I2C_WRITE_FS_SCL_LCNT(controller, lo_cnt);
488 #if HAS_SS_I2C_FAST_PLUS_SPEED
490 QM_SS_I2C_WRITE_SPKLEN(controller, QM_SS_I2C_SPK_LEN_FSP);
491 QM_SS_I2C_WRITE_SPEED(controller, QM_SS_I2C_CON_SPEED_FSP);
493 QM_SS_I2C_CLEAR_FS_SCL_HCNT(controller);
494 QM_SS_I2C_CLEAR_FS_SCL_LCNT(controller);
496 QM_SS_I2C_WRITE_FS_SCL_HCNT(controller, hi_cnt);
497 QM_SS_I2C_WRITE_FS_SCL_LCNT(controller, lo_cnt);
508 QM_CHECK(status != NULL, -EINVAL);
510 uint32_t controller = i2c_base[i2c];
515 if (QM_SS_I2C_READ_STATUS(controller) & QM_SS_I2C_STATUS_BUSY_MASK) {
520 *status |= (QM_SS_I2C_READ_TX_ABRT_SOURCE(controller) &
521 QM_SS_I2C_TX_ABRT_SOURCE_ALL_MASK);
527 const uint8_t *
const data, uint32_t len,
530 QM_CHECK(i2c < QM_SS_I2C_NUM, -EINVAL);
531 QM_CHECK(data != NULL, -EINVAL);
532 QM_CHECK(len > 0, -EINVAL);
534 uint8_t *d = (uint8_t *)data;
535 uint32_t controller = i2c_base[i2c], data_cmd = 0;
539 QM_SS_I2C_CLEAR_TAR(controller);
540 QM_SS_I2C_WRITE_TAR(controller, slave_addr);
543 controller_enable(i2c);
548 while (!(QM_SS_I2C_READ_STATUS(controller) &
549 QM_SS_I2C_STATUS_TFNF))
555 data_cmd |= QM_SS_I2C_DATA_CMD_PUSH;
558 if (len == 0 && stop) {
559 data_cmd |= QM_SS_I2C_DATA_CMD_STOP;
562 QM_SS_I2C_WRITE_DATA_CMD(controller, data_cmd);
568 while (!(QM_SS_I2C_READ_STATUS(controller) & QM_SS_I2C_STATUS_TFE))
571 if ((QM_SS_I2C_READ_INTR_STAT(controller) &
572 QM_SS_I2C_INTR_STAT_TX_ABRT)) {
578 if (controller_disable(i2c)) {
583 if (status != NULL) {
593 QM_SS_I2C_CLEAR_TX_ABRT_INTR(controller);
599 uint8_t *
const data, uint32_t len,
const bool stop,
602 QM_CHECK(i2c < QM_SS_I2C_NUM, -EINVAL);
603 QM_CHECK(data != NULL, -EINVAL);
604 QM_CHECK(len > 0, -EINVAL);
606 uint32_t controller = i2c_base[i2c],
607 data_cmd = QM_SS_I2C_DATA_CMD_CMD | QM_SS_I2C_DATA_CMD_PUSH;
608 uint8_t *d = (uint8_t *)data;
612 QM_SS_I2C_CLEAR_TAR(controller);
613 QM_SS_I2C_WRITE_TAR(controller, slave_addr);
616 controller_enable(i2c);
619 if (len == 0 && stop) {
620 data_cmd |= QM_SS_I2C_DATA_CMD_STOP;
623 QM_SS_I2C_WRITE_DATA_CMD(controller, data_cmd);
627 while (!(QM_SS_I2C_READ_STATUS(controller) &
628 QM_SS_I2C_STATUS_RFNE)) {
629 if (QM_SS_I2C_READ_INTR_STAT(controller) &
630 QM_SS_I2C_INTR_STAT_TX_ABRT) {
635 if ((QM_SS_I2C_READ_INTR_STAT(controller) &
636 QM_SS_I2C_INTR_STAT_TX_ABRT)) {
641 QM_SS_I2C_READ_RX_FIFO(controller);
645 (QM_SS_I2C_READ_STATUS(controller) & QM_SS_I2C_STATUS_RFNE))
649 *d = QM_SS_I2C_READ_DATA_CMD(controller);
655 if (controller_disable(i2c)) {
660 if (status != NULL) {
670 QM_SS_I2C_CLEAR_TX_ABRT_INTR(controller);
677 const uint16_t slave_addr)
679 QM_CHECK(i2c < QM_SS_I2C_NUM, -EINVAL);
680 QM_CHECK(NULL != xfer, -EINVAL);
682 uint32_t controller = i2c_base[i2c];
685 QM_SS_I2C_CLEAR_TAR(controller);
686 QM_SS_I2C_WRITE_TAR(controller, slave_addr);
688 i2c_write_pos[i2c] = 0;
689 i2c_read_pos[i2c] = 0;
690 i2c_read_cmd_send[i2c] = xfer->
rx_len;
691 i2c_transfer[i2c] = xfer;
699 QM_SS_I2C_CLEAR_RX_TL(controller);
700 QM_SS_I2C_CLEAR_TX_TL(controller);
702 QM_SS_I2C_WRITE_RX_TL(controller, (xfer->
rx_len - 1));
703 QM_SS_I2C_WRITE_TX_TL(controller, TX_TL);
705 QM_SS_I2C_CLEAR_RX_TL(controller);
706 QM_SS_I2C_CLEAR_TX_TL(controller);
708 QM_SS_I2C_WRITE_RX_TL(controller, RX_TL);
709 QM_SS_I2C_WRITE_TX_TL(controller, TX_TL);
713 controller_enable(i2c);
716 i2c_fill_tx_fifo(i2c, xfer, controller);
719 QM_SS_I2C_UNMASK_INTERRUPTS(controller);
724 static void controller_enable(
const qm_ss_i2c_t i2c)
726 uint32_t controller = i2c_base[i2c];
727 if (!(QM_SS_I2C_READ_ENABLE_STATUS(controller) &
728 QM_SS_I2C_ENABLE_STATUS_IC_EN)) {
730 QM_SS_I2C_ENABLE(controller);
732 while (!(QM_SS_I2C_READ_ENABLE_STATUS(controller) &
733 QM_SS_I2C_ENABLE_STATUS_IC_EN))
738 QM_SS_I2C_CLEAR_ALL_INTR(controller);
741 static int controller_disable(
const qm_ss_i2c_t i2c)
743 uint32_t controller = i2c_base[i2c];
744 int poll_count = I2C_POLL_COUNT;
747 QM_SS_I2C_DISABLE(controller);
750 while ((QM_SS_I2C_READ_ENABLE_STATUS(controller) &
751 QM_SS_I2C_ENABLE_STATUS_IC_EN) &&
757 return (QM_SS_I2C_READ_ENABLE_STATUS(controller) &
758 QM_SS_I2C_ENABLE_STATUS_IC_EN);
763 QM_CHECK(i2c < QM_SS_I2C_NUM, -EINVAL);
765 uint32_t controller = i2c_base[i2c];
776 QM_SS_I2C_ABORT(controller);
781 #if (ENABLE_RESTORE_CONTEXT)
785 uint32_t controller = i2c_base[i2c];
787 QM_CHECK(i2c < QM_SS_I2C_NUM, -EINVAL);
788 QM_CHECK(ctx != NULL, -EINVAL);
790 ctx->i2c_fs_scl_cnt =
791 __builtin_arc_lr(controller + QM_SS_I2C_FS_SCL_CNT);
792 ctx->i2c_ss_scl_cnt =
793 __builtin_arc_lr(controller + QM_SS_I2C_SS_SCL_CNT);
794 ctx->i2c_con = __builtin_arc_lr(controller + QM_SS_I2C_CON);
802 uint32_t controller = i2c_base[i2c];
804 QM_CHECK(i2c < QM_SS_I2C_NUM, -EINVAL);
805 QM_CHECK(ctx != NULL, -EINVAL);
807 __builtin_arc_sr(ctx->i2c_fs_scl_cnt,
808 controller + QM_SS_I2C_FS_SCL_CNT);
809 __builtin_arc_sr(ctx->i2c_ss_scl_cnt,
810 controller + QM_SS_I2C_SS_SCL_CNT);
811 __builtin_arc_sr(ctx->i2c_con, controller + QM_SS_I2C_CON);
qm_ss_i2c_speed_t
QM SS I2C speed type.
int qm_ss_i2c_master_write(const qm_ss_i2c_t i2c, const uint16_t slave_addr, const uint8_t *const data, uint32_t len, const bool stop, qm_ss_i2c_status_t *const status)
Master write on I2C.
int qm_ss_i2c_master_irq_transfer(const qm_ss_i2c_t i2c, const qm_ss_i2c_transfer_t *const xfer, const uint16_t slave_addr)
Interrupt based master transfer on I2C.
int qm_ss_i2c_save_context(const qm_ss_i2c_t i2c, qm_ss_i2c_context_t *const ctx)
Save SS I2C context.
QM_ISR_DECLARE(qm_ss_i2c_0_error_isr)
ISR for I2C 0 error interrupt.
qm_ss_i2c_t
Sensor Subsystem I2C.
uint32_t rx_len
Read buffer length.
void(* callback)(void *data, int rc, qm_ss_i2c_status_t status, uint32_t len)
User callback.
int qm_ss_i2c_get_status(const qm_ss_i2c_t i2c, qm_ss_i2c_status_t *const status)
Retrieve SS I2C status.
Standard mode (100 Kbps).
void clk_sys_udelay(uint32_t microseconds)
Idle loop the processor for at least the value given in microseconds.
uint32_t clk_sys_get_ticks_per_us(void)
Get number of system ticks per micro second.
qm_ss_i2c_status_t
QM SS I2C status type.
int qm_ss_i2c_master_read(const qm_ss_i2c_t i2c, const uint16_t slave_addr, uint8_t *const data, uint32_t len, const bool stop, qm_ss_i2c_status_t *const status)
Master read of I2C.
qm_i2c_t
Number of I2C controllers.
int qm_ss_i2c_set_speed(const qm_ss_i2c_t i2c, const qm_ss_i2c_speed_t speed, const uint16_t lo_cnt, const uint16_t hi_cnt)
Set I2C speed.
qm_ss_i2c_speed_t speed
Standard, fast or fast plus mode.
QM SS I2C configuration type.
int qm_ss_i2c_restore_context(const qm_ss_i2c_t i2c, const qm_ss_i2c_context_t *const ctx)
Restore SS I2C context.
int qm_ss_i2c_set_config(const qm_ss_i2c_t i2c, const qm_ss_i2c_config_t *const cfg)
Set SS I2C configuration.
uint32_t tx_len
Write data length.
int qm_ss_i2c_irq_transfer_terminate(const qm_ss_i2c_t i2c)
Terminate I2C IRQ/DMA transfer.
qm_ss_i2c_addr_t address_mode
7 or 10 bit addressing.