5 #include "qm_aon_counters.h"
7 #if (HAS_SOC_CONTEXT_RETENTION)
8 #include "power_states.h"
11 static void (*callback[QM_AONC_NUM])(
void *) = {NULL};
12 static void *callback_data[QM_AONC_NUM];
16 #if (NUM_AONC_CONTROLLERS > 1)
22 #define BUSY_CHECK(_aonc)
27 static void wait_single_cycle(
const qm_aonc_t aonc)
29 uint32_t aonc_cfg, initial_cnt;
32 aonc_cfg = QM_AONC[aonc]->aonc_cfg;
33 QM_AONC[aonc]->aonc_cfg |= QM_AONC_ENABLE;
34 initial_cnt = QM_AONC[aonc]->aonc_cnt;
36 while (initial_cnt == QM_AONC[aonc]->aonc_cnt) {
39 QM_AONC[aonc]->aonc_cfg = aonc_cfg;
44 #define CLEAR_CHECK(_aonc) \
45 while (QM_AONC[(_aonc)]->aonpt_ctrl & QM_AONPT_CLR) { \
47 wait_single_cycle(_aonc);
49 #define RESET_CHECK(_aonc) \
50 while (QM_AONC[(_aonc)]->aonpt_ctrl & QM_AONPT_RST) { \
52 wait_single_cycle(_aonc);
54 #define CLEAR_CHECK(_aonc) \
55 while (QM_AONC[(_aonc)]->aonpt_ctrl & QM_AONPT_CLR) { \
58 #define RESET_CHECK(_aonc) \
59 while (QM_AONC[(_aonc)]->aonpt_ctrl & QM_AONPT_RST) { \
63 #define AONPT_CLEAR(_aonc) \
65 QM_AONC[(_aonc)]->aonpt_ctrl |= QM_AONPT_CLR; \
70 static __inline__
void pt_reset(
const qm_aonc_t aonc)
74 static bool first_run =
true;
84 aonc_cfg = QM_AONC[aonc]->aonc_cfg;
85 QM_AONC[aonc]->aonc_cfg |= QM_AONC_ENABLE;
87 while (0 == QM_AONC[aonc]->aonc_cnt) {
90 QM_AONC[aonc]->aonc_cfg = aonc_cfg;
95 QM_AONC[aonc]->aonpt_ctrl |= QM_AONPT_RST;
101 #define AONPT_RESET(_aonc) pt_reset((_aonc))
107 #if (HAS_SOC_CONTEXT_RETENTION)
108 if (QM_SCSS_GP->gps0 & QM_GPS0_POWER_STATES_MASK) {
117 for (aonc = QM_AONC_0; aonc < QM_AONC_NUM; aonc++) {
118 if ((QM_AONC[aonc]->aonpt_stat & QM_AONPT_INTERRUPT)) {
119 if (callback[aonc]) {
120 (*callback[aonc])(callback_data[aonc]);
127 QM_ISR_EOI(QM_IRQ_AONPT_0_INT_VECTOR);
132 QM_CHECK(aonc < QM_AONC_NUM, -EINVAL);
133 QM_CHECK(aonc >= QM_AONC_0, -EINVAL);
135 QM_AONC[aonc]->aonc_cfg = QM_AONC_ENABLE;
142 QM_CHECK(aonc < QM_AONC_NUM, -EINVAL);
143 QM_CHECK(aonc >= QM_AONC_0, -EINVAL);
145 QM_AONC[aonc]->aonc_cfg = QM_AONC_DISABLE;
152 QM_CHECK(aonc < QM_AONC_NUM, -EINVAL);
153 QM_CHECK(aonc >= QM_AONC_0, -EINVAL);
154 QM_CHECK(val != NULL, -EINVAL);
156 *val = QM_AONC[aonc]->aonc_cnt;
163 QM_CHECK(aonc < QM_AONC_NUM, -EINVAL);
164 QM_CHECK(aonc >= QM_AONC_0, -EINVAL);
165 QM_CHECK(cfg != NULL, -EINVAL);
167 QM_AONC[aonc]->aonpt_cfg = cfg->
count;
176 callback[aonc] = NULL;
186 QM_CHECK(aonc < QM_AONC_NUM, -EINVAL);
187 QM_CHECK(aonc >= QM_AONC_0, -EINVAL);
188 QM_CHECK(val != NULL, -EINVAL);
190 *val = QM_AONC[aonc]->aonpt_cnt;
197 QM_CHECK(aonc < QM_AONC_NUM, -EINVAL);
198 QM_CHECK(aonc >= QM_AONC_0, -EINVAL);
199 QM_CHECK(status != NULL, -EINVAL);
201 if (QM_AONC[aonc]->aonpt_stat & QM_AONPT_INTERRUPT) {
212 QM_CHECK(aonc < QM_AONC_NUM, -EINVAL);
213 QM_CHECK(aonc >= QM_AONC_0, -EINVAL);
226 QM_CHECK(aonc < QM_AONC_NUM, -EINVAL);
227 QM_CHECK(aonc >= QM_AONC_0, -EINVAL);
234 #if (ENABLE_RESTORE_CONTEXT)
237 QM_CHECK(aonc < QM_AONC_NUM, -EINVAL);
238 QM_CHECK(ctx != NULL, -EINVAL);
247 const qm_aonc_context_t *
const ctx)
249 uint32_t int_aonpt_mask;
250 QM_CHECK(aonc < QM_AONC_NUM, -EINVAL);
251 QM_CHECK(ctx != NULL, -EINVAL);
265 int_aonpt_mask = QM_INTERRUPT_ROUTER->aonpt_0_int_mask;
266 QM_INTERRUPT_ROUTER->aonpt_0_int_mask = 0xFFFFFFFF;
267 QM_INTERRUPT_ROUTER->aonpt_0_int_mask = int_aonpt_mask;
281 const qm_aonc_context_t *
const ctx)
int qm_aonc_disable(const qm_aonc_t aonc)
Disable the Always-on Counter.
void qm_power_soc_restore(void)
Restore system state after sleep or deep sleep.
int qm_aonpt_clear(const qm_aonc_t aonc)
Clear the status of the Always-on Periodic Timer.
uint32_t count
Time to count down from in clock cycles.
void(* callback)(void *data)
User callback.
QM_ISR_DECLARE(qm_aonpt_0_isr)
ISR for Always-on Periodic Timer 0 interrupt.
void * callback_data
Callback data.
qm_aonpt_status_t
Always on counter status.
int qm_aonc_enable(const qm_aonc_t aonc)
Enable the Always-on Counter.
int qm_aonpt_get_status(const qm_aonc_t aonc, qm_aonpt_status_t *const status)
Get the current status of an Always-on Periodic Timer.
int qm_aonc_get_value(const qm_aonc_t aonc, uint32_t *const val)
Get the current value of the Always-on Counter.
Always-on Counter Controller register map.
int qm_aonpt_save_context(const qm_aonc_t aonc, qm_aonc_context_t *const ctx)
Save the Always-on Periodic Timer context.
int qm_aonpt_get_value(const qm_aonc_t aonc, uint32_t *const val)
Get the current value of the Always-on Periodic Timer.
bool int_en
Enable/disable the interrupts.
QM Always-on Periodic Timer configuration type.
int qm_aonpt_reset(const qm_aonc_t aonc)
Reset the Always-on Periodic Timer back to the configured value.
int qm_aonpt_set_config(const qm_aonc_t aonc, const qm_aonpt_config_t *const cfg)
Set the Always-on Periodic Timer configuration.
int qm_aonpt_restore_context(const qm_aonc_t aonc, const qm_aonc_context_t *const ctx)
Restore the Always-on Periodic Timer context.
qm_aonc_t
Number of Always-on counter controllers.