Intel® Quark™ Microcontroller Software Interface
1.4.0
Intel® Quark™ Microcontroller BSP
Main Page
Modules
Data Structures
Files
File List
qm_soc_interrupts.h
1
/*
2
* {% copyright %}
3
*/
4
5
#ifndef __QM_SOC_INTERRUPTS_H__
6
#define __QM_SOC_INTERRUPTS_H__
7
8
#include "qm_common.h"
9
10
/**
11
* Quark D2000 SoC Interrupts.
12
*
13
* @defgroup groupQUARKD2000SEINT SoC Interrupts (D2000)
14
* @{
15
*/
16
17
/* x86 internal interrupt vectors. */
18
#define QM_X86_DIVIDE_ERROR_INT (0)
19
#define QM_X86_DEBUG_EXCEPTION_INT (1)
20
#define QM_X86_NMI_INTERRUPT_INT (2)
21
#define QM_X86_BREAKPOINT_INT (3)
22
#define QM_X86_OVERFLOW_INT (4)
23
#define QM_X86_BOUND_RANGE_EXCEEDED_INT (5)
24
#define QM_X86_INVALID_OPCODE_INT (6)
25
#define QM_X86_DEVICE_NOT_AVAILABLE_INT (7)
26
#define QM_X86_DOUBLE_FAULT_INT (8)
27
#define QM_X86_INTEL_RESERVED_09_INT (9)
28
#define QM_X86_INVALID_TSS_INT (10)
29
#define QM_X86_SEGMENT_NOT_PRESENT_INT (11)
30
#define QM_X86_STACK_SEGMENT_FAULT_INT (12)
31
#define QM_X86_GENERAL_PROTECT_FAULT_INT (13)
32
#define QM_X86_PAGE_FAULT_INT (14)
33
#define QM_X86_INTEL_RESERVED_15_INT (15)
34
#define QM_X86_FLOATING_POINT_ERROR_INT (16)
35
#define QM_X86_ALIGNMENT_CHECK_INT (17)
36
#define QM_X86_INTEL_RESERVED_18_INT (18)
37
#define QM_X86_INTEL_RESERVED_19_INT (19)
38
#define QM_X86_INTEL_RESERVED_20_INT (20)
39
#define QM_X86_INTEL_RESERVED_21_INT (21)
40
#define QM_X86_INTEL_RESERVED_22_INT (22)
41
#define QM_X86_INTEL_RESERVED_23_INT (23)
42
#define QM_X86_INTEL_RESERVED_24_INT (24)
43
#define QM_X86_INTEL_RESERVED_25_INT (25)
44
#define QM_X86_INTEL_RESERVED_26_INT (26)
45
#define QM_X86_INTEL_RESERVED_27_INT (27)
46
#define QM_X86_INTEL_RESERVED_28_INT (28)
47
#define QM_X86_INTEL_RESERVED_29_INT (29)
48
#define QM_X86_INTEL_RESERVED_30_INT (30)
49
#define QM_X86_INTEL_RESERVED_31_INT (31)
50
51
/* IRQs and interrupt vectors.
52
*
53
* The vector numbers must be defined without arithmetic expressions nor
54
* parentheses because they are expanded as token concatenation.
55
*/
56
57
#define QM_IRQ_DMA_0_ERROR_INT 0
58
#define QM_IRQ_DMA_0_ERROR_INT_MASK_OFFSET 28
59
#define QM_IRQ_DMA_0_ERROR_INT_VECTOR 32
60
61
#define QM_IRQ_HOST_BUS_ERROR_INT 1
62
#define QM_IRQ_HOST_BUS_ERROR_INT_MASK_OFFSET 29
63
#define QM_IRQ_HOST_BUS_ERROR_INT_VECTOR 33
64
65
#define QM_IRQ_RTC_0_INT 2
66
#define QM_IRQ_RTC_0_INT_MASK_OFFSET 12
67
#define QM_IRQ_RTC_0_INT_VECTOR 34
68
69
#define QM_IRQ_AONPT_0_INT 3
70
#define QM_IRQ_AONPT_0_INT_MASK_OFFSET 32
71
#define QM_IRQ_AONPT_0_INT_VECTOR 35
72
73
#define QM_IRQ_I2C_0_INT 4
74
#define QM_IRQ_I2C_0_INT_MASK_OFFSET 0
75
#define QM_IRQ_I2C_0_INT_VECTOR 36
76
77
#define QM_IRQ_SPI_SLAVE_0_INT 5
78
#define QM_IRQ_SPI_SLAVE_0_INT_MASK_OFFSET 5
79
#define QM_IRQ_SPI_SLAVE_0_INT_VECTOR 37
80
81
#define QM_IRQ_UART_1_INT 6
82
#define QM_IRQ_UART_1_INT_MASK_OFFSET 7
83
#define QM_IRQ_UART_1_INT_VECTOR 38
84
85
#define QM_IRQ_SPI_MASTER_0_INT 7
86
#define QM_IRQ_SPI_MASTER_0_INT_MASK_OFFSET 3
87
#define QM_IRQ_SPI_MASTER_0_INT_VECTOR 39
88
89
#define QM_IRQ_UART_0_INT 8
90
#define QM_IRQ_UART_0_INT_MASK_OFFSET 6
91
#define QM_IRQ_UART_0_INT_VECTOR 40
92
93
#define QM_IRQ_ADC_0_CAL_INT 9
94
#define QM_IRQ_ADC_0_CAL_INT_MASK_OFFSET 34
95
#define QM_IRQ_ADC_0_CAL_INT_VECTOR 41
96
97
#define QM_IRQ_PIC_TIMER 10
98
/* No SCSS mask register for PIC timer: point to an unused register */
99
#define QM_IRQ_PIC_TIMER_MASK_OFFSET 1
100
#define QM_IRQ_PIC_TIMER_VECTOR 42
101
102
#define QM_IRQ_PWM_0_INT 11
103
#define QM_IRQ_PWM_0_INT_MASK_OFFSET 10
104
#define QM_IRQ_PWM_0_INT_VECTOR 43
105
106
#define QM_IRQ_DMA_0_INT_1 12
107
#define QM_IRQ_DMA_0_INT_1_MASK_OFFSET 15
108
#define QM_IRQ_DMA_0_INT_1_VECTOR 44
109
110
#define QM_IRQ_DMA_0_INT_0 13
111
#define QM_IRQ_DMA_0_INT_0_MASK_OFFSET 14
112
#define QM_IRQ_DMA_0_INT_0_VECTOR 45
113
114
#define QM_IRQ_COMPARATOR_0_INT 14
115
#define QM_IRQ_COMPARATOR_0_INT_MASK_OFFSET 26
116
#define QM_IRQ_COMPARATOR_0_INT_VECTOR 46
117
118
#define QM_IRQ_GPIO_0_INT 15
119
#define QM_IRQ_GPIO_0_INT_MASK_OFFSET 9
120
#define QM_IRQ_GPIO_0_INT_VECTOR 47
121
122
#define QM_IRQ_WDT_0_INT 16
123
#define QM_IRQ_WDT_0_INT_MASK_OFFSET 13
124
#define QM_IRQ_WDT_0_INT_VECTOR 48
125
126
#define QM_IRQ_SRAM_MPR_0_INT 17
127
#define QM_IRQ_SRAM_MPR_0_INT_MASK_OFFSET 29
128
#define QM_IRQ_SRAM_MPR_0_INT_VECTOR 49
129
130
#define QM_IRQ_FLASH_MPR_0_INT 18
131
#define QM_IRQ_FLASH_MPR_0_INT_MASK_OFFSET 30
132
#define QM_IRQ_FLASH_MPR_0_INT_VECTOR 50
133
134
#define QM_IRQ_ADC_0_PWR_INT 19
135
#define QM_IRQ_ADC_0_PWR_INT_MASK_OFFSET 33
136
#define QM_IRQ_ADC_0_PWR_INT_VECTOR 51
137
138
/** @} */
139
140
#endif
/* __QM_SOC_INTERRUPTS_H__ */
soc
quark_d2000
include
qm_soc_interrupts.h
Generated on Tue Mar 7 2017 21:59:18 for Intel® Quark™ Microcontroller Software Interface by
1.8.6