Intel® Quark™ Microcontroller Software Interface
1.4.0
Intel® Quark™ Microcontroller BSP
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System Core register map. More...
#include <qm_soc_regs.h>
Data Fields | |
QM_RW uint32_t | osc0_cfg0 |
Hybrid Oscillator Configuration 0. More... | |
QM_RW uint32_t | osc0_stat1 |
Hybrid Oscillator status 1. More... | |
QM_RW uint32_t | osc0_cfg1 |
Hybrid Oscillator configuration 1. More... | |
QM_RW uint32_t | osc1_stat0 |
RTC Oscillator status 0. More... | |
QM_RW uint32_t | osc1_cfg0 |
RTC Oscillator Configuration 0. More... | |
QM_RW uint32_t | ccu_periph_clk_gate_ctl |
Peripheral Clock Gate Control. More... | |
QM_RW uint32_t | ccu_periph_clk_div_ctl0 |
Peripheral Clock Divider Control 0. More... | |
QM_RW uint32_t | ccu_gpio_db_clk_ctl |
Peripheral Clock Divider Control 1. More... | |
QM_RW uint32_t | ccu_ext_clock_ctl |
External Clock Control Register. More... | |
QM_RW uint32_t | ccu_lp_clk_ctl |
System Low Power Clock Control. More... | |
QM_RW uint32_t | wake_mask |
Wake Mask register. More... | |
QM_RW uint32_t | ccu_mlayer_ahb_ctl |
AHB Control Register. More... | |
QM_RW uint32_t | ccu_sys_clk_ctl |
System Clock Control Register. More... | |
QM_RW uint32_t | osc_lock_0 |
Clocks Lock Register. More... | |
QM_RW uint32_t | soc_ctrl |
SoC Control Register. More... | |
QM_RW uint32_t | soc_ctrl_lock |
SoC Control Register Lock. More... | |
QM_RW uint32_t | usb_pll_cfg0 |
USB Phase lock look configuration. More... | |
QM_RW uint32_t | ccu_ss_periph_clk_gate_ctl |
Sensor Subsystem peripheral clock gate control. More... | |
System Core register map.
Definition at line 30 of file qm_soc_regs.h.
QM_RW uint32_t qm_scss_ccu_reg_t::ccu_ext_clock_ctl |
External Clock Control Register.
Definition at line 44 of file qm_soc_regs.h.
QM_RW uint32_t qm_scss_ccu_reg_t::ccu_gpio_db_clk_ctl |
Peripheral Clock Divider Control 1.
Definition at line 42 of file qm_soc_regs.h.
QM_RW uint32_t qm_scss_ccu_reg_t::ccu_lp_clk_ctl |
System Low Power Clock Control.
Definition at line 46 of file qm_soc_regs.h.
QM_RW uint32_t qm_scss_ccu_reg_t::ccu_mlayer_ahb_ctl |
AHB Control Register.
Definition at line 48 of file qm_soc_regs.h.
QM_RW uint32_t qm_scss_ccu_reg_t::ccu_periph_clk_div_ctl0 |
Peripheral Clock Divider Control 0.
Peripheral Clock Divider Control.
0
Definition at line 40 of file qm_soc_regs.h.
QM_RW uint32_t qm_scss_ccu_reg_t::ccu_periph_clk_gate_ctl |
Peripheral Clock Gate Control.
Definition at line 38 of file qm_soc_regs.h.
QM_RW uint32_t qm_scss_ccu_reg_t::ccu_ss_periph_clk_gate_ctl |
Sensor Subsystem peripheral clock gate control.
Definition at line 52 of file qm_soc_regs.h.
QM_RW uint32_t qm_scss_ccu_reg_t::ccu_sys_clk_ctl |
System Clock Control Register.
Definition at line 49 of file qm_soc_regs.h.
QM_RW uint32_t qm_scss_ccu_reg_t::osc0_cfg0 |
Hybrid Oscillator Configuration 0.
Definition at line 31 of file qm_soc_regs.h.
QM_RW uint32_t qm_scss_ccu_reg_t::osc0_cfg1 |
Hybrid Oscillator configuration 1.
Definition at line 33 of file qm_soc_regs.h.
QM_RW uint32_t qm_scss_ccu_reg_t::osc0_stat1 |
Hybrid Oscillator status 1.
Definition at line 32 of file qm_soc_regs.h.
QM_RW uint32_t qm_scss_ccu_reg_t::osc1_cfg0 |
RTC Oscillator Configuration 0.
Definition at line 35 of file qm_soc_regs.h.
QM_RW uint32_t qm_scss_ccu_reg_t::osc1_stat0 |
RTC Oscillator status 0.
Definition at line 34 of file qm_soc_regs.h.
QM_RW uint32_t qm_scss_ccu_reg_t::osc_lock_0 |
Clocks Lock Register.
Definition at line 50 of file qm_soc_regs.h.
QM_RW uint32_t qm_scss_ccu_reg_t::soc_ctrl |
SoC Control Register.
Definition at line 51 of file qm_soc_regs.h.
QM_RW uint32_t qm_scss_ccu_reg_t::soc_ctrl_lock |
SoC Control Register Lock.
Definition at line 52 of file qm_soc_regs.h.
QM_RW uint32_t qm_scss_ccu_reg_t::usb_pll_cfg0 |
USB Phase lock look configuration.
Definition at line 42 of file qm_soc_regs.h.
QM_RW uint32_t qm_scss_ccu_reg_t::wake_mask |
Wake Mask register.
Definition at line 47 of file qm_soc_regs.h.