5 #ifndef __QM_INTERRUPT_ROUTER_REGS_H__
6 #define __QM_INTERRUPT_ROUTER_REGS_H__
20 #define QM_IR_INT_LMT_MASK BIT(0)
23 #define QM_IR_INT_LMT_HALT_MASK BIT(16)
29 #define QM_IR_LMT_INT_LOCK_HALT_MASK(_peripheral_) \
30 (QM_INTERRUPT_ROUTER->lock_int_mask_reg & BIT(2))
31 #define QM_IR_LMT_INT_LOCK_MASK(_peripheral_) \
32 (QM_INTERRUPT_ROUTER->lock_int_mask_reg & BIT(0))
35 #define QM_IR_UNMASK_LMT_INTERRUPTS(_peripheral_) \
36 (_peripheral_ &= ~(QM_IR_INT_LMT_MASK))
39 #define QM_IR_MASK_LMT_INTERRUPTS(_peripheral_) \
40 (_peripheral_ |= QM_IR_INT_LMT_MASK)
43 #define QM_IR_UNMASK_LMT_HALTS(_peripheral_) \
44 (_peripheral_ &= ~(QM_IR_INT_LMT_HALT_MASK))
47 #define QM_IR_MASK_LMT_HALTS(_peripheral_) \
48 (_peripheral_ |= QM_IR_INT_LMT_HALT_MASK)
50 #define QM_IR_GET_LMT_MASK(_peripheral_) (_peripheral_ & QM_IR_INT_LMT_MASK)
51 #define QM_IR_GET_LMT_HALT_MASK(_peripheral_) \
52 (_peripheral_ & QM_IR_INT_LMT_HALT_MASK)
56 #define QM_IR_UNMASK_INTERRUPTS(_peripheral_) \
57 QM_IR_UNMASK_LMT_INTERRUPTS(_peripheral_)
58 #define QM_IR_MASK_INTERRUPTS(_peripheral_) \
59 QM_IR_MASK_LMT_INTERRUPTS(_peripheral_)
60 #define QM_IR_UNMASK_HALTS(_peripheral_) QM_IR_UNMASK_LMT_HALTS(_peripheral_)
61 #define QM_IR_MASK_HALTS(_peripheral_) QM_IR_MASK_LMT_HALTS(_peripheral_)
63 #define QM_IR_INT_LOCK_MASK(_peripheral_) QM_IR_LMT_INT_LOCK_MASK(_peripheral_)
64 #define QM_IR_INT_LOCK_HALT_MASK(_peripheral_) \
65 QM_IR_LMT_INT_LOCK_MASK(_peripheral_)
67 #define QM_IR_INT_MASK QM_IR_INT_LMT_MASK
68 #define QM_IR_INT_HALT_MASK QM_IR_INT_LMT_HALT_MASK
69 #define QM_IR_GET_MASK(_peripheral_) QM_IR_GET_LMT_MASK(_peripheral_)
70 #define QM_IR_GET_HALT_MASK(_peripheral_) QM_IR_GET_LMT_HALT_MASK(_peripheral_)
73 #error "No active core selected."
79 QM_R uint32_t reserved[2];
81 QM_R uint32_t reserved1;
85 QM_RW uint32_t reserved2;
88 QM_R uint32_t reserved3;
93 QM_RW uint32_t reserved4[8];
96 QM_R uint32_t reserved5;
103 QM_R uint32_t reserved6;
107 QM_R uint32_t reserved7;
112 #define QM_INTERRUPT_ROUTER_MASK_NUMREG \
113 ((sizeof(qm_interrupt_router_reg_t) / sizeof(uint32_t)) - 1)
116 #define QM_INTERRUPT_ROUTER_MASK_DEFAULT (0xFFFFFFFF)
120 #define QM_INTERRUPT_ROUTER \
121 ((qm_interrupt_router_reg_t *)(&test_interrupt_router))
124 #define QM_INTERRUPT_ROUTER_BASE (0xB0800448)
125 #define QM_INTERRUPT_ROUTER \
126 ((qm_interrupt_router_reg_t *)QM_INTERRUPT_ROUTER_BASE)
129 #define QM_IR_DMA_ERROR_HOST_MASK (0x00000003)
QM_RW uint32_t dma_0_error_int_mask
DMA 0 Error, Mask 28.
QM_RW uint32_t i2c_master_0_int_mask
I2C Master 0, Mask 0.
QM_RW uint32_t sram_mpr_0_int_mask
SRAM MPR 0, Mask 29.
QM_RW uint32_t dma_0_int_0_mask
DMA 0 int 0, Mask 14.
QM_RW uint32_t uart_0_int_mask
UART 0, Mask 6.
QM_RW uint32_t aonpt_0_int_mask
AONPT 0, Mask 32.
QM_RW uint32_t adc_0_pwr_int_mask
ADC 0 PWR, Mask 33.
QM_RW uint32_t dma_0_int_1_mask
DMA 0 int 1, Mask 15.
QM_RW uint32_t gpio_0_int_mask
GPIO 0, Mask 9.
QM_RW uint32_t wdt_0_int_mask
WDT 0, Mask 13.
QM_RW uint32_t rtc_0_int_mask
RTC 0, Mask 12.
QM_RW uint32_t comparator_0_host_halt_int_mask
Comparator 0 Host halt, Mask 24.
QM_RW uint32_t timer_0_int_mask
Timer 0, Mask 10.
QM_RW uint32_t spi_master_0_int_mask
SPI Master 0, Mask 3.
QM_RW uint32_t spi_slave_0_int_mask
SPI Slave 0, Mask 5.
QM_RW uint32_t lock_int_mask_reg
Interrupt Mask Lock Register.
QM_RW uint32_t adc_0_cal_int_mask
ADC 0 CAL, Mask 34.
QM_RW uint32_t host_bus_error_int_mask
Host bus error, Mask 27.
QM_RW uint32_t uart_1_int_mask
UART 1, Mask 7.
QM_RW uint32_t comparator_0_host_int_mask
Comparator 0 Host, Mask 26.
QM_RW uint32_t flash_mpr_0_int_mask
Flash MPR 0, Mask 30.