5 #ifndef __QM_INTERRUPT_ROUTER_REGS_H__
6 #define __QM_INTERRUPT_ROUTER_REGS_H__
20 #define QM_IR_INT_LMT_MASK BIT(0)
21 #define QM_IR_INT_SS_MASK BIT(8)
24 #define QM_IR_INT_LMT_HALT_MASK BIT(16)
25 #define QM_IR_INT_SS_HALT_MASK BIT(24)
31 #define QM_IR_SS_INT_LOCK_HALT_MASK(_peripheral_) \
32 (QM_INTERRUPT_ROUTER->lock_int_mask_reg & BIT(3))
33 #define QM_IR_LMT_INT_LOCK_HALT_MASK(_peripheral_) \
34 (QM_INTERRUPT_ROUTER->lock_int_mask_reg & BIT(2))
35 #define QM_IR_SS_INT_LOCK_MASK(_peripheral_) \
36 (QM_INTERRUPT_ROUTER->lock_int_mask_reg & BIT(1))
37 #define QM_IR_LMT_INT_LOCK_MASK(_peripheral_) \
38 (QM_INTERRUPT_ROUTER->lock_int_mask_reg & BIT(0))
41 #define QM_IR_UNMASK_LMT_INTERRUPTS(_peripheral_) \
42 (_peripheral_ &= ~(QM_IR_INT_LMT_MASK))
43 #define QM_IR_UNMASK_SS_INTERRUPTS(_peripheral_) \
44 (_peripheral_ &= ~(QM_IR_INT_SS_MASK))
47 #define QM_IR_MASK_LMT_INTERRUPTS(_peripheral_) \
48 (_peripheral_ |= QM_IR_INT_LMT_MASK)
49 #define QM_IR_MASK_SS_INTERRUPTS(_peripheral_) \
50 (_peripheral_ |= QM_IR_INT_SS_MASK)
53 #define QM_IR_UNMASK_LMT_HALTS(_peripheral_) \
54 (_peripheral_ &= ~(QM_IR_INT_LMT_HALT_MASK))
55 #define QM_IR_UNMASK_SS_HALTS(_peripheral_) \
56 (_peripheral_ &= ~(QM_IR_INT_SS_HALT_MASK))
59 #define QM_IR_MASK_LMT_HALTS(_peripheral_) \
60 (_peripheral_ |= QM_IR_INT_LMT_HALT_MASK)
61 #define QM_IR_MASK_SS_HALTS(_peripheral_) \
62 (_peripheral_ |= QM_IR_INT_SS_HALT_MASK)
64 #define QM_IR_GET_LMT_MASK(_peripheral_) (_peripheral_ & QM_IR_INT_LMT_MASK)
65 #define QM_IR_GET_LMT_HALT_MASK(_peripheral_) \
66 (_peripheral_ & QM_IR_INT_LMT_HALT_MASK)
68 #define QM_IR_GET_SS_MASK(_peripheral_) (_peripheral_ & QM_IR_INT_SS_MASK)
69 #define QM_IR_GET_SS_HALT_MASK(_peripheral_) \
70 (_peripheral_ & QM_IR_INT_SS_HALT_MASK)
79 #define QM_IR_MBOX_ENABLE_LMT_INT_MASK(N) \
80 QM_INTERRUPT_ROUTER->mailbox_0_int_mask &= \
81 ~(BIT(N + QM_MBOX_HOST_MASK_OFFSET))
82 #define QM_IR_MBOX_DISABLE_LMT_INT_MASK(N) \
83 QM_INTERRUPT_ROUTER->mailbox_0_int_mask |= \
84 (BIT(N + QM_MBOX_HOST_MASK_OFFSET))
85 #define QM_IR_MBOX_ENABLE_SS_INT_MASK(N) \
86 QM_INTERRUPT_ROUTER->mailbox_0_int_mask &= \
87 ~(BIT(N + QM_MBOX_SS_MASK_OFFSET))
88 #define QM_IR_MBOX_DISABLE_SS_INT_MASK(N) \
89 QM_INTERRUPT_ROUTER->mailbox_0_int_mask |= \
90 (BIT(N + QM_MBOX_SS_MASK_OFFSET))
100 #define QM_IR_MBOX_ENABLE_LMT_INT_HALT_MASK(N) \
101 QM_INTERRUPT_ROUTER->mailbox_0_int_mask &= \
102 ~(BIT(N + QM_MBOX_HOST_HALT_MASK_OFFSET))
103 #define QM_IR_MBOX_DISABLE_LMT_INT_HALT_MASK(N) \
104 QM_INTERRUPT_ROUTER->mailbox_0_int_mask |= \
105 (BIT(N + QM_MBOX_HOST_HALT_MASK_OFFSET))
106 #define QM_IR_MBOX_ENABLE_SS_INT_HALT_MASK(N) \
107 QM_INTERRUPT_ROUTER->mailbox_0_int_mask &= \
108 ~(BIT(N + QM_MBOX_SS_HALT_MASK_OFFSET))
109 #define QM_IR_MBOX_DISABLE_SS_INT_HALT_MASK(N) \
110 QM_INTERRUPT_ROUTER->mailbox_0_int_mask |= \
111 (BIT(N + QM_MBOX_SS_HALT_MASK_OFFSET))
116 #define QM_IR_MBOX_SS_INT_HALT_MASK \
117 ((QM_MBOX_SS_HALT_MASK_MASK & \
118 QM_INTERRUPT_ROUTER->mailbox_0_int_mask) >> \
119 QM_MBOX_SS_HALT_MASK_OFFSET)
120 #define QM_IR_MBOX_LMT_INT_HALT_MASK \
121 ((QM_MBOX_HOST_HALT_MASK_MASK & \
122 QM_INTERRUPT_ROUTER->mailbox_0_int_mask) >> \
123 QM_MBOX_SS_HALT_MASK_OFFSET)
124 #define QM_IR_MBOX_SS_ALL_INT_MASK \
125 ((QM_MBOX_SS_MASK_MASK & QM_INTERRUPT_ROUTER->mailbox_0_int_mask) >> \
126 QM_MBOX_SS_MASK_OFFSET)
127 #define QM_IR_MBOX_LMT_ALL_INT_MASK \
128 (QM_MBOX_HOST_MASK_MASK & QM_INTERRUPT_ROUTER->mailbox_0_int_mask)
134 #define QM_IR_MBOX_SS_INT_LOCK_HALT_MASK(N) \
135 (QM_INTERRUPT_ROUTER->lock_int_mask_reg & BIT(3))
136 #define QM_IR_MBOX_LMT_INT_LOCK_HALT_MASK(N) \
137 (QM_INTERRUPT_ROUTER->lock_int_mask_reg & BIT(2))
138 #define QM_IR_MBOX_SS_INT_LOCK_MASK(N) \
139 (QM_INTERRUPT_ROUTER->lock_int_mask_reg & BIT(1))
140 #define QM_IR_MBOX_LMT_INT_LOCK_MASK(N) \
141 (QM_INTERRUPT_ROUTER->lock_int_mask_reg & BIT(0))
146 #define QM_IR_MBOX_IS_LMT_INT_MASK_EN(N) \
147 ~(QM_IR_MBOX_LMT_ALL_INT_MASK & ((1 << (N))))
148 #define QM_IR_MBOX_IS_SS_INT_MASK_EN(N) \
149 ~(QM_IR_MBOX_SS_ALL_INT_MASK & ((1 << (QM_MBOX_SS_MASK_OFFSET + (N)))))
151 #define QM_IR_UNMASK_COMPARATOR_LMT_INTERRUPTS(n) \
152 (QM_INTERRUPT_ROUTER->comparator_0_host_int_mask &= ~(BIT(n)))
153 #define QM_IR_MASK_COMPARATOR_LMT_INTERRUPTS(n) \
154 (QM_INTERRUPT_ROUTER->comparator_0_host_int_mask |= BIT(n))
155 #define QM_IR_UNMASK_COMPARATOR_LMT_HALTS(n) \
156 (QM_INTERRUPT_ROUTER->comparator_0_host_halt_int_mask &= ~(BIT(n)))
157 #define QM_IR_MASK_COMPARATOR_LMT_HALTS(n) \
158 (QM_INTERRUPT_ROUTER->comparator_0_host_halt_int_mask |= BIT(n))
160 #define QM_IR_UNMASK_COMPARATOR_SS_INTERRUPTS(n) \
161 (QM_INTERRUPT_ROUTER->comparator_0_ss_int_mask &= ~(BIT(n)))
162 #define QM_IR_MASK_COMPARATOR_SS_INTERRUPTS(n) \
163 (QM_INTERRUPT_ROUTER->comparator_0_ss_int_mask |= BIT(n))
164 #define QM_IR_UNMASK_COMPARATOR_SS_HALTS(n) \
165 (QM_INTERRUPT_ROUTER->comparator_0_ss_halt_int_mask &= ~(BIT(n)))
166 #define QM_IR_MASK_COMPARATOR_SS_HALTS(n) \
167 (QM_INTERRUPT_ROUTER->comparator_0_ss_halt_int_mask |= BIT(n))
171 #define QM_IR_UNMASK_INTERRUPTS(_peripheral_) \
172 QM_IR_UNMASK_LMT_INTERRUPTS(_peripheral_)
173 #define QM_IR_MASK_INTERRUPTS(_peripheral_) \
174 QM_IR_MASK_LMT_INTERRUPTS(_peripheral_)
175 #define QM_IR_UNMASK_HALTS(_peripheral_) QM_IR_UNMASK_LMT_HALTS(_peripheral_)
176 #define QM_IR_MASK_HALTS(_peripheral_) QM_IR_MASK_LMT_HALTS(_peripheral_)
178 #define QM_IR_INT_LOCK_MASK(_peripheral_) QM_IR_LMT_INT_LOCK_MASK(_peripheral_)
179 #define QM_IR_INT_LOCK_HALT_MASK(_peripheral_) \
180 QM_IR_LMT_INT_LOCK_MASK(_peripheral_)
182 #define QM_IR_INT_MASK QM_IR_INT_LMT_MASK
183 #define QM_IR_INT_HALT_MASK QM_IR_INT_LMT_HALT_MASK
184 #define QM_IR_GET_MASK(_peripheral_) QM_IR_GET_LMT_MASK(_peripheral_)
185 #define QM_IR_GET_HALT_MASK(_peripheral_) QM_IR_GET_LMT_HALT_MASK(_peripheral_)
187 #define QM_IR_UNMASK_COMPARATOR_INTERRUPTS(n) \
188 QM_IR_UNMASK_COMPARATOR_LMT_INTERRUPTS(n)
189 #define QM_IR_MASK_COMPARATOR_INTERRUPTS(n) \
190 QM_IR_MASK_COMPARATOR_LMT_INTERRUPTS(n)
191 #define QM_IR_UNMASK_COMPARATOR_HALTS(n) QM_IR_UNMASK_COMPARATOR_LMT_HALTS(n)
192 #define QM_IR_MASK_COMPARATOR_HALTS(n) QM_IR_MASK_COMPARATOR_LMT_HALTS(n)
195 #define QM_IR_UNMASK_INTERRUPTS(_peripheral_) \
196 QM_IR_UNMASK_SS_INTERRUPTS(_peripheral_)
197 #define QM_IR_MASK_INTERRUPTS(_peripheral_) \
198 QM_IR_MASK_SS_INTERRUPTS(_peripheral_)
199 #define QM_IR_UNMASK_HALTS(_peripheral_) QM_IR_UNMASK_SS_HALTS(_peripheral_)
200 #define QM_IR_MASK_HALTS(_peripheral_) QM_IR_MASK_SS_HALTS(_peripheral_)
202 #define QM_IR_INT_LOCK_MASK(_peripheral_) QM_IR_SS_INT_LOCK_MASK(_peripheral_)
203 #define QM_IR_INT_LOCK_HALT_MASK(_peripheral_) \
204 QM_IR_SS_INT_LOCK_MASK(_peripheral_)
206 #define QM_IR_INT_MASK QM_IR_INT_SS_MASK
207 #define QM_IR_INT_HALT_MASK QM_IR_INT_SS_HALT_MASK
208 #define QM_IR_GET_MASK(_peripheral_) QM_IR_GET_SS_MASK(_peripheral_)
209 #define QM_IR_GET_HALT_MASK(_peripheral_) QM_IR_GET_SS_HALT_MASK(_peripheral_)
211 #define QM_IR_UNMASK_COMPARATOR_INTERRUPTS(n) \
212 QM_IR_UNMASK_COMPARATOR_SS_INTERRUPTS(n)
213 #define QM_IR_MASK_COMPARATOR_INTERRUPTS(n) \
214 QM_IR_MASK_COMPARATOR_SS_INTERRUPTS(n)
215 #define QM_IR_UNMASK_COMPARATOR_HALTS(n) QM_IR_UNMASK_COMPARATOR_SS_HALTS(n)
216 #define QM_IR_MASK_COMPARATOR_HALTS(n) QM_IR_MASK_COMPARATOR_SS_HALTS(n)
219 #error "No active core selected."
224 QM_RW uint32_t err_mask;
225 QM_RW uint32_t rx_avail_mask;
226 QM_RW uint32_t tx_req_mask;
227 QM_RW uint32_t stop_det_mask;
232 QM_RW uint32_t err_int_mask;
233 QM_RW uint32_t rx_avail_mask;
234 QM_RW uint32_t tx_req_mask;
247 QM_RW uint32_t i2c_master_0_int_mask;
249 QM_R uint32_t reserved;
250 QM_RW uint32_t spi_master_0_int_mask;
252 QM_RW uint32_t spi_slave_0_int_mask;
253 QM_RW uint32_t uart_0_int_mask;
254 QM_RW uint32_t uart_1_int_mask;
256 QM_RW uint32_t gpio_0_int_mask;
259 QM_RW uint32_t rtc_0_int_mask;
260 QM_RW uint32_t wdt_0_int_mask;
261 QM_RW uint32_t dma_0_int_0_mask;
262 QM_RW uint32_t dma_0_int_1_mask;
274 QM_RW uint32_t comparator_0_host_halt_int_mask;
278 QM_RW uint32_t comparator_0_host_int_mask;
279 QM_RW uint32_t host_bus_error_int_mask;
280 QM_RW uint32_t dma_0_error_int_mask;
281 QM_RW uint32_t sram_mpr_0_int_mask;
282 QM_RW uint32_t flash_mpr_0_int_mask;
284 QM_RW uint32_t aonpt_0_int_mask;
285 QM_RW uint32_t adc_0_pwr_int_mask;
286 QM_RW uint32_t adc_0_cal_int_mask;
288 QM_RW uint32_t lock_int_mask_reg;
292 #define QM_INTERRUPT_ROUTER_MASK_NUMREG \
293 ((sizeof(qm_interrupt_router_reg_t) / sizeof(uint32_t)) - 1)
296 #define QM_INTERRUPT_ROUTER_MASK_DEFAULT (0xFFFFFFFF)
300 #define QM_INTERRUPT_ROUTER \
301 ((qm_interrupt_router_reg_t *)(&test_interrupt_router))
305 #define QM_INTERRUPT_ROUTER_BASE (0xB0800400)
306 #define QM_INTERRUPT_ROUTER \
307 ((qm_interrupt_router_reg_t *)QM_INTERRUPT_ROUTER_BASE)
310 #define QM_IR_DMA_ERROR_HOST_MASK (0x000000FF)
311 #define QM_IR_DMA_ERROR_SS_MASK (0x0000FF00)
314 #define QM_IR_DMA_ERROR_MASK QM_IR_DMA_ERROR_HOST_MASK
316 #define QM_IR_DMA_ERROR_MASK QM_IR_DMA_ERROR_SS_MASK
QM_RW uint32_t i2c_master_1_int_mask
I2C Master 1.
QM_RW uint32_t aon_gpio_0_int_mask
AON GPIO 0.
QM_RW uint32_t i2s_0_int_mask
I2S 0.
QM_RW uint32_t ss_gpio_1_int_mask
Sensor GPIO 1.
SS I2C Interrupt register map.
QM_RW uint32_t dma_0_int_5_mask
DMA 0 Ch 5.
QM_RW uint32_t dma_0_int_3_mask
DMA 0 Ch 3.
QM_RW uint32_t dma_0_int_2_mask
DMA 0 Ch 2.
QM_RW uint32_t ss_adc_0_error_int_mask
Sensor ADC 0 Error.
QM_RW uint32_t dma_0_int_7_mask
DMA 0 Ch 7.
QM_RW uint32_t flash_mpr_1_int_mask
Flash MPR 1.
SS SPI Interrupt register map.
int_ss_i2c_reg_t ss_i2c_1_int
Sensor I2C 1 Masks.
QM_RW uint32_t ss_adc_0_int_mask
Sensor ADC 0.
QM_RW uint32_t ss_gpio_0_int_mask
Sensor GPIO 0.
int_ss_spi_reg_t ss_spi_0_int
Sensor SPI 0 Masks.
QM_RW uint32_t usb_0_int_mask
USB 0.
QM_RW uint32_t dma_0_int_6_mask
DMA 0 Ch 6.
QM_RW uint32_t pwm_0_int_mask
PWM 0.
QM_RW uint32_t spi_master_1_int_mask
SPI Master 1.
QM_RW uint32_t comparator_0_ss_halt_int_mask
Comparator Sensor Halt Mask.
int_ss_i2c_reg_t ss_i2c_0_int
Sensor I2C 0 Masks.
int_ss_spi_reg_t ss_spi_1_int
Sensor SPI 1 Masks.
QM_RW uint32_t dma_0_int_4_mask
DMA 0 Ch 4.
QM_RW uint32_t mailbox_0_int_mask
Mailbox 0 Combined 8 Channel Host and Sensor Masks.
QM_RW uint32_t comparator_0_ss_int_mask
Comparator Sensor Mask.