8 #define MASK_1BIT (0x1)
9 #define MASK_2BIT (0x3)
19 static uint32_t pin_to_register(uint32_t pin, uint32_t width)
21 return (pin / (32 / width));
32 static uint32_t pin_to_offset(uint32_t pin, uint32_t width)
34 return ((pin % (32 / width)) * width);
39 QM_CHECK(pin < QM_PIN_ID_NUM, -EINVAL);
42 uint32_t reg = pin_to_register(pin, 2);
43 uint32_t offs = pin_to_offset(pin, 2);
45 QM_SCSS_PMUX->pmux_sel[reg] &= ~(MASK_2BIT << offs);
46 QM_SCSS_PMUX->pmux_sel[reg] |= (fn << offs);
53 QM_CHECK(pin < QM_PIN_ID_NUM, -EINVAL);
56 uint32_t reg = pin_to_register(pin, 1);
57 uint32_t mask = MASK_1BIT << pin_to_offset(pin, 1);
60 QM_SCSS_PMUX->pmux_slew[reg] &= ~mask;
62 QM_SCSS_PMUX->pmux_slew[reg] |= mask;
69 QM_CHECK(pin < QM_PIN_ID_NUM, -EINVAL);
71 uint32_t reg = pin_to_register(pin, 1);
72 uint32_t mask = MASK_1BIT << pin_to_offset(pin, 1);
74 if (enable ==
false) {
75 QM_SCSS_PMUX->pmux_in_en[reg] &= ~mask;
77 QM_SCSS_PMUX->pmux_in_en[reg] |= mask;
84 QM_CHECK(pin < QM_PIN_ID_NUM, -EINVAL);
86 uint32_t reg = pin_to_register(pin, 1);
87 uint32_t mask = MASK_1BIT << pin_to_offset(pin, 1);
89 if (enable ==
false) {
90 QM_SCSS_PMUX->pmux_pullup[reg] &= ~mask;
92 QM_SCSS_PMUX->pmux_pullup[reg] |= mask;
qm_pin_id_t
External Pad pin identifiers.
Max number of slew rate options.
int qm_pmux_input_en(const qm_pin_id_t pin, const bool enable)
Enable input for a pin in the pin mux controller.
qm_pmux_slew_t
Pin slew rate setting.
int qm_pmux_select(const qm_pin_id_t pin, const qm_pmux_fn_t fn)
Set up pin muxing for a SoC pin.
int qm_pmux_set_slew(const qm_pin_id_t pin, const qm_pmux_slew_t slew)
Set up pin's slew rate in the pin mux controller.
int qm_pmux_pullup_en(const qm_pin_id_t pin, const bool enable)
Enable pullup for a pin in the pin mux controller.
qm_pmux_fn_t
Pin function type.