11 #define SPK_LEN_SS (1)
12 #define SPK_LEN_FS_FSP (2)
15 #define I2C_POLL_COUNT (1000000)
16 #define I2C_POLL_MICROSECOND (1)
28 static volatile uint32_t i2c_write_pos[QM_I2C_NUM], i2c_read_pos[QM_I2C_NUM],
29 i2c_read_cmd_send[QM_I2C_NUM];
32 static volatile bool transfer_ongoing;
33 static volatile bool first_start;
47 static volatile bool is_addressed =
false;
61 volatile bool ongoing_dma_tx_operation;
62 volatile bool ongoing_dma_rx_operation;
68 i2c_dma_context_t i2c_dma_context[QM_I2C_NUM];
81 static void i2c_dma_transmit_callback(
void *callback_context, uint32_t len,
83 static void i2c_dma_receive_callback(
void *callback_context, uint32_t len,
85 static int i2c_start_dma_read(
const qm_i2c_t i2c);
86 void *i2c_dma_callbacks[] = {NULL, i2c_dma_transmit_callback,
87 i2c_dma_receive_callback};
89 static void controller_enable(
const qm_i2c_t i2c);
90 static int controller_disable(
const qm_i2c_t i2c);
98 static void empty_rx_fifo(
const qm_i2c_t i2c,
102 while (controller->
ic_status & QM_I2C_IC_STATUS_RFNE) {
103 if (!transfer_ongoing) {
107 if (transfer->
rx_len > i2c_read_pos[i2c]) {
108 transfer->
rx[i2c_read_pos[i2c]++] =
112 if (transfer->
rx_len == i2c_read_pos[i2c]) {
117 transfer_ongoing =
false;
135 static void slave_fill_tx_fifo(
const qm_i2c_t i2c,
139 while ((controller->
ic_status & QM_I2C_IC_STATUS_TNF) &&
140 (!(controller->
ic_intr_stat & QM_I2C_IC_INTR_STAT_TX_ABRT))) {
141 if (!transfer_ongoing) {
146 if (transfer->
tx_len > i2c_write_pos[i2c]) {
148 transfer->
tx[i2c_write_pos[i2c]++];
151 if (transfer->
tx_len == i2c_write_pos[i2c]) {
156 transfer_ongoing =
false;
168 static __inline__
int handle_tx_abrt_common(
qm_i2c_reg_t *
const controller,
174 QM_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT));
191 static __inline__
void
192 handle_irq_tx_abrt(
const qm_i2c_t i2c,
199 rc = handle_tx_abrt_common(controller, &status);
201 controller_disable(i2c);
208 static __inline__
void handle_dma_tx_abrt(
const qm_i2c_t i2c,
214 rc = handle_tx_abrt_common(controller, &status);
217 i2c_dma_context[i2c].tx_abort_status = status;
218 i2c_dma_context[i2c].i2c_error_code = rc;
226 static __inline__
void
227 i2c_isr_slave_handler(
const qm_i2c_t i2c,
245 if (ic_intr_stat & QM_I2C_IC_INTR_STAT_STOP_DETECTED) {
247 empty_rx_fifo(i2c, transfer, controller);
256 if ((transfer->
stop ==
true) &&
257 (is_addressed || (i2c_read_pos[i2c] != 0))) {
258 controller_disable(i2c);
264 (transfer_ongoing) ? i2c_read_pos[i2c] : 0);
266 i2c_write_pos[i2c] = 0;
267 i2c_read_pos[i2c] = 0;
269 controller->
ic_intr_mask &= ~QM_I2C_IC_INTR_MASK_TX_EMPTY;
271 is_addressed =
false;
289 if (ic_intr_stat & QM_I2C_IC_INTR_STAT_START_DETECTED) {
291 empty_rx_fifo(i2c, transfer, controller);
296 (transfer_ongoing) ? i2c_read_pos[i2c] : 0);
298 transfer_ongoing =
true;
299 i2c_write_pos[i2c] = 0;
300 i2c_read_pos[i2c] = 0;
319 if (ic_intr_stat & QM_I2C_IC_INTR_STAT_RX_OVER) {
328 if (ic_intr_stat & QM_I2C_IC_INTR_STAT_RX_FULL) {
330 empty_rx_fifo(i2c, transfer, controller);
350 else if (ic_intr_stat & QM_I2C_IC_INTR_STAT_RD_REQ) {
357 slave_fill_tx_fifo(i2c, transfer, controller);
360 controller->
ic_intr_mask |= QM_I2C_IC_INTR_MASK_TX_EMPTY;
361 }
else if (ic_intr_stat & QM_I2C_IC_INTR_STAT_RX_DONE) {
367 controller->
ic_intr_mask &= ~QM_I2C_IC_INTR_MASK_TX_EMPTY;
375 }
else if (ic_intr_stat & QM_I2C_IC_INTR_STAT_TX_EMPTY) {
376 slave_fill_tx_fifo(i2c, transfer, controller);
380 else if (ic_intr_stat & QM_I2C_IC_INTR_STAT_GEN_CALL_DETECTED) {
392 QM_I2C_IC_INTR_STAT_GEN_CALL_DETECTED) {
406 master_fill_tx_fifo(
const qm_i2c_t i2c,
410 uint32_t ic_data_cmd, count_tx = (QM_I2C_FIFO_SIZE - TX_TL);
411 uint32_t write_buffer_remaining = transfer->
tx_len - i2c_write_pos[i2c];
412 uint32_t read_buffer_remaining = transfer->
rx_len - i2c_read_pos[i2c];
414 while ((count_tx) && write_buffer_remaining) {
416 write_buffer_remaining--;
422 ic_data_cmd = transfer->
tx[i2c_write_pos[i2c]];
428 if (transfer->
stop && (write_buffer_remaining == 0) &&
429 (read_buffer_remaining == 0)) {
431 ic_data_cmd |= QM_I2C_IC_DATA_CMD_STOP_BIT_CTRL;
436 i2c_write_pos[i2c]++;
444 return write_buffer_remaining;
447 static __inline__
void
448 i2c_isr_master_handler(
const qm_i2c_t i2c,
453 uint32_t read_buffer_remaining = transfer->
rx_len - i2c_read_pos[i2c];
454 uint32_t write_buffer_remaining = transfer->
tx_len - i2c_write_pos[i2c];
455 uint32_t missing_bytes;
458 if (controller->
ic_intr_stat & QM_I2C_IC_INTR_STAT_RX_FULL) {
460 while (read_buffer_remaining && controller->
ic_rxflr) {
461 transfer->
rx[i2c_read_pos[i2c]] =
463 read_buffer_remaining--;
466 if (read_buffer_remaining == 0) {
472 ~(QM_I2C_IC_INTR_MASK_RX_FULL |
473 QM_I2C_IC_INTR_MASK_TX_EMPTY);
475 if (transfer->
stop) {
476 controller_disable(i2c);
487 if (read_buffer_remaining > 0 &&
488 read_buffer_remaining < (RX_TL + 1)) {
494 controller->
ic_rx_tl = read_buffer_remaining - 1;
503 if (controller->
ic_intr_stat & QM_I2C_IC_INTR_STAT_TX_EMPTY) {
505 if ((controller->
ic_status & QM_I2C_IC_STATUS_TFE) &&
506 (transfer->
tx != NULL) && (write_buffer_remaining == 0) &&
507 (read_buffer_remaining == 0)) {
510 ~QM_I2C_IC_INTR_MASK_TX_EMPTY;
516 if (transfer->
stop) {
517 controller_disable(i2c);
528 write_buffer_remaining =
529 master_fill_tx_fifo(i2c, transfer, controller);
538 missing_bytes = read_buffer_remaining - i2c_read_cmd_send[i2c];
544 QM_ASSERT(controller->
ic_rxflr <= missing_bytes);
547 count_tx = QM_I2C_FIFO_SIZE - controller->
ic_txflr;
549 if (count_tx > missing_bytes) {
550 count_tx -= missing_bytes;
555 while (i2c_read_cmd_send[i2c] &&
556 (write_buffer_remaining == 0) && count_tx) {
558 i2c_read_cmd_send[i2c]--;
564 if (transfer->
stop && (i2c_read_cmd_send[i2c] == 0)) {
566 QM_I2C_IC_DATA_CMD_READ |
567 QM_I2C_IC_DATA_CMD_STOP_BIT_CTRL;
570 QM_I2C_IC_DATA_CMD_READ;
575 if ((write_buffer_remaining == 0) &&
576 (read_buffer_remaining == 0)) {
582 static void i2c_isr_irq_handler(
const qm_i2c_t i2c)
588 if (controller->
ic_intr_stat & QM_I2C_IC_INTR_STAT_TX_OVER) {
595 controller_disable(i2c);
603 if (controller->
ic_intr_stat & QM_I2C_IC_INTR_STAT_RX_UNDER) {
610 controller_disable(i2c);
623 (QM_I2C_IC_INTR_STAT_TX_ABRT | QM_I2C_IC_INTR_STAT_RX_DONE)) ==
624 QM_I2C_IC_INTR_STAT_TX_ABRT) {
625 handle_irq_tx_abrt(i2c, transfer, controller);
629 if (controller->
ic_con & QM_I2C_IC_CON_MASTER_MODE) {
631 if (controller->
ic_intr_stat & QM_I2C_IC_INTR_STAT_RX_OVER) {
638 controller_disable(i2c);
645 i2c_isr_master_handler(i2c, transfer, controller);
649 i2c_isr_slave_handler(i2c, transfer, controller);
653 static void i2c_isr_dma_handler(
const qm_i2c_t i2c)
659 if (controller->
ic_intr_stat & QM_I2C_IC_INTR_STAT_TX_OVER) {
666 controller_disable(i2c);
673 if (controller->
ic_intr_stat & QM_I2C_IC_INTR_STAT_RX_UNDER) {
680 controller_disable(i2c);
687 if (controller->
ic_intr_stat & QM_I2C_IC_INTR_STAT_RX_OVER) {
694 controller_disable(i2c);
706 if (controller->
ic_intr_stat & QM_I2C_IC_INTR_STAT_TX_ABRT) {
707 handle_dma_tx_abrt(i2c, controller);
713 i2c_isr_irq_handler(QM_I2C_0);
714 QM_ISR_EOI(QM_IRQ_I2C_0_INT_VECTOR);
719 i2c_isr_dma_handler(QM_I2C_0);
720 QM_ISR_EOI(QM_IRQ_I2C_0_INT_VECTOR);
726 i2c_isr_irq_handler(QM_I2C_1);
727 QM_ISR_EOI(QM_IRQ_I2C_1_INT_VECTOR);
732 i2c_isr_dma_handler(QM_I2C_1);
733 QM_ISR_EOI(QM_IRQ_I2C_1_INT_VECTOR);
737 static uint32_t get_lo_cnt(uint32_t lo_time_ns)
742 static uint32_t get_hi_cnt(
qm_i2c_t i2c, uint32_t hi_time_ns)
745 QM_I2C[i2c]->ic_fs_spklen) +
751 uint32_t lcnt = 0, hcnt = 0, min_lcnt = 0, lcnt_diff = 0, ic_con = 0;
752 QM_CHECK(i2c < QM_I2C_NUM, -EINVAL);
753 QM_CHECK(cfg != NULL, -EINVAL);
757 i2c_dma_context[i2c].ongoing_dma_rx_operation =
false;
758 i2c_dma_context[i2c].ongoing_dma_tx_operation =
false;
763 if (controller_disable(i2c)) {
770 ic_con = QM_I2C_IC_CON_MASTER_MODE | QM_I2C_IC_CON_RESTART_EN |
771 QM_I2C_IC_CON_SLAVE_DISABLE |
774 << QM_I2C_IC_CON_10BITADDR_MASTER_OFFSET);
784 switch (cfg->
speed) {
787 ic_con |= QM_I2C_IC_CON_SPEED_SS;
791 min_lcnt = get_lo_cnt(QM_I2C_MIN_SS_NS);
792 lcnt = get_lo_cnt(QM_I2C_SS_50_DC_NS);
793 hcnt = get_hi_cnt(i2c, QM_I2C_SS_50_DC_NS);
797 ic_con |= QM_I2C_IC_CON_SPEED_FS_FSP;
801 min_lcnt = get_lo_cnt(QM_I2C_MIN_FS_NS);
802 lcnt = get_lo_cnt(QM_I2C_FS_50_DC_NS);
803 hcnt = get_hi_cnt(i2c, QM_I2C_FS_50_DC_NS);
807 ic_con |= QM_I2C_IC_CON_SPEED_FS_FSP;
811 min_lcnt = get_lo_cnt(QM_I2C_MIN_FSP_NS);
812 lcnt = get_lo_cnt(QM_I2C_FSP_50_DC_NS);
813 hcnt = get_hi_cnt(i2c, QM_I2C_FSP_50_DC_NS);
817 if (hcnt > QM_I2C_IC_HCNT_MAX || hcnt < QM_I2C_IC_HCNT_MIN) {
821 if (lcnt > QM_I2C_IC_LCNT_MAX || lcnt < QM_I2C_IC_LCNT_MIN) {
827 if (lcnt < min_lcnt) {
828 lcnt_diff = (min_lcnt - lcnt);
850 << QM_I2C_IC_CON_10BITADDR_SLAVE_OFFSET;
855 ic_con |= QM_I2C_IC_CON_STOP_DET_IFADDRESSED;
863 controller->
ic_con = ic_con;
868 const uint16_t lo_cnt,
const uint16_t hi_cnt)
870 QM_CHECK(i2c < QM_I2C_NUM, -EINVAL);
871 QM_CHECK(hi_cnt < QM_I2C_IC_HCNT_MAX && lo_cnt > QM_I2C_IC_HCNT_MIN,
873 QM_CHECK(lo_cnt < QM_I2C_IC_LCNT_MAX && lo_cnt > QM_I2C_IC_LCNT_MIN,
878 uint32_t ic_con = controller->
ic_con;
879 ic_con &= ~QM_I2C_IC_CON_SPEED_MASK;
883 ic_con |= QM_I2C_IC_CON_SPEED_SS;
891 ic_con |= QM_I2C_IC_CON_SPEED_FS_FSP;
898 controller->
ic_con = ic_con;
905 QM_CHECK(i2c < QM_I2C_NUM, -EINVAL);
906 QM_CHECK(status != NULL, -EINVAL);
913 if (controller->
ic_status & QM_I2C_IC_STATUS_BUSY_MASK) {
925 const uint8_t *
const data, uint32_t len,
928 uint8_t *d = (uint8_t *)data;
929 uint32_t ic_data_cmd = 0;
932 QM_CHECK(i2c < QM_I2C_NUM, -EINVAL);
933 QM_CHECK(slave_addr <= QM_I2C_IC_TAR_MASK, -EINVAL);
934 QM_CHECK(data != NULL, -EINVAL);
935 QM_CHECK(len > 0, -EINVAL);
940 controller->
ic_tar &= ~QM_I2C_IC_TAR_MASK;
941 controller->
ic_tar |= slave_addr;
944 controller_enable(i2c);
949 while (!(controller->
ic_status & QM_I2C_IC_STATUS_TNF))
959 if (len == 0 && stop) {
960 ic_data_cmd |= QM_I2C_IC_DATA_CMD_STOP_BIT_CTRL;
970 while (!(controller->
ic_status & QM_I2C_IC_STATUS_TFE))
979 if (controller_disable(i2c)) {
984 if (status != NULL) {
1000 uint8_t *
const data, uint32_t len,
const bool stop,
1003 uint8_t *d = (uint8_t *)data;
1006 QM_CHECK(i2c < QM_I2C_NUM, -EINVAL);
1007 QM_CHECK(slave_addr <= QM_I2C_IC_TAR_MASK, -EINVAL);
1008 QM_CHECK(data != NULL, -EINVAL);
1009 QM_CHECK(len > 0, -EINVAL);
1014 controller->
ic_tar &= ~QM_I2C_IC_TAR_MASK;
1015 controller->
ic_tar |= slave_addr;
1018 controller_enable(i2c);
1021 if (len == 0 && stop) {
1023 QM_I2C_IC_DATA_CMD_READ |
1024 QM_I2C_IC_DATA_CMD_STOP_BIT_CTRL;
1029 controller->
ic_data_cmd = QM_I2C_IC_DATA_CMD_READ;
1033 while (!(controller->
ic_status & QM_I2C_IC_STATUS_RFNE)) {
1036 QM_I2C_IC_RAW_INTR_STAT_TX_ABRT) {
1042 QM_I2C_IC_TX_ABRT_SOURCE_ALL_MASK) {
1053 if (controller_disable(i2c)) {
1058 if (status != NULL) {
1075 const uint16_t slave_addr)
1077 QM_CHECK(i2c < QM_I2C_NUM, -EINVAL);
1078 QM_CHECK(NULL != xfer, -EINVAL);
1079 QM_CHECK(slave_addr <= QM_I2C_IC_TAR_MASK, -EINVAL);
1084 controller->
ic_tar &= ~QM_I2C_IC_TAR_MASK;
1085 controller->
ic_tar |= slave_addr;
1087 i2c_write_pos[i2c] = 0;
1088 i2c_read_pos[i2c] = 0;
1089 i2c_read_cmd_send[i2c] = xfer->
rx_len;
1090 i2c_transfer[i2c] = xfer;
1106 QM_I2C[i2c]->ic_intr_mask = QM_I2C_IC_INTR_MASK_ALL;
1109 controller_enable(i2c);
1112 master_fill_tx_fifo(i2c, xfer, controller);
1116 QM_I2C_IC_INTR_MASK_RX_UNDER | QM_I2C_IC_INTR_MASK_RX_OVER |
1117 QM_I2C_IC_INTR_MASK_RX_FULL | QM_I2C_IC_INTR_MASK_TX_OVER |
1118 QM_I2C_IC_INTR_MASK_TX_EMPTY | QM_I2C_IC_INTR_MASK_TX_ABORT;
1126 QM_CHECK(i2c < QM_I2C_NUM, -EINVAL);
1127 QM_CHECK(xfer != NULL, -EINVAL);
1132 i2c_transfer[i2c] = xfer;
1133 i2c_write_pos[i2c] = 0;
1134 i2c_read_pos[i2c] = 0;
1136 transfer_ongoing =
false;
1137 is_addressed =
false;
1146 controller_enable(i2c);
1155 QM_I2C_IC_INTR_MASK_RX_UNDER | QM_I2C_IC_INTR_MASK_RX_OVER |
1156 QM_I2C_IC_INTR_MASK_RX_FULL | QM_I2C_IC_INTR_MASK_TX_ABORT |
1157 QM_I2C_IC_INTR_MASK_RX_DONE | QM_I2C_IC_INTR_MASK_STOP_DETECTED |
1158 QM_I2C_IC_INTR_MASK_START_DETECTED | QM_I2C_IC_INTR_MASK_RD_REQ |
1159 QM_I2C_IC_INTR_MASK_GEN_CALL_DETECTED;
1167 QM_CHECK(i2c < QM_I2C_NUM, -EINVAL);
1168 QM_CHECK(xfer != NULL, -EINVAL);
1171 i2c_transfer[i2c] = xfer;
1172 i2c_write_pos[i2c] = 0;
1173 i2c_read_pos[i2c] = 0;
1176 transfer_ongoing =
true;
1181 static void controller_enable(
const qm_i2c_t i2c)
1187 controller->
ic_enable |= QM_I2C_IC_ENABLE_CONTROLLER_EN;
1191 QM_I2C_IC_ENABLE_STATUS_IC_EN))
1199 static int controller_disable(
const qm_i2c_t i2c)
1202 int poll_count = I2C_POLL_COUNT;
1205 controller->
ic_enable &= ~QM_I2C_IC_ENABLE_CONTROLLER_EN;
1219 QM_CHECK(i2c < QM_I2C_NUM, -EINVAL);
1227 QM_I2C[i2c]->ic_enable |= QM_I2C_IC_ENABLE_CONTROLLER_ABORT;
1239 QM_CHECK(i2c < QM_I2C_NUM, -EINVAL);
1241 if (i2c_dma_context[i2c].ongoing_dma_tx_operation) {
1244 i2c_dma_context[i2c].dma_controller_id,
1245 i2c_dma_context[i2c].dma_tx_channel_id);
1248 if (i2c_dma_context[i2c].ongoing_dma_rx_operation) {
1251 i2c_dma_context[i2c].dma_controller_id,
1252 i2c_dma_context[i2c].dma_rx_channel_id);
1266 static void i2c_dma_transfer_error_callback(uint32_t i2c,
int error_code,
1271 if (error_code != 0) {
1272 if (i2c_dma_context[i2c].ongoing_dma_tx_operation ==
true) {
1274 QM_I2C[i2c]->ic_dma_cr &= ~QM_I2C_IC_DMA_CR_TX_ENABLE;
1275 i2c_dma_context[i2c].ongoing_dma_tx_operation =
false;
1278 if (i2c_dma_context[i2c].ongoing_dma_rx_operation ==
true) {
1280 QM_I2C[i2c]->ic_dma_cr &= ~QM_I2C_IC_DMA_CR_RX_ENABLE;
1281 i2c_dma_context[i2c].ongoing_dma_rx_operation =
false;
1285 controller_disable(i2c);
1290 i2c_dma_context[i2c].tx_abort_status,
1301 static void i2c_dma_transmit_callback(
void *callback_context, uint32_t len,
1306 qm_i2c_t i2c = ((i2c_dma_context_t *)callback_context)->i2c;
1309 if ((error_code == 0) && (i2c_dma_context[i2c].i2c_error_code == 0)) {
1311 QM_I2C[i2c]->ic_dma_cr &= ~QM_I2C_IC_DMA_CR_TX_ENABLE;
1312 i2c_dma_context[i2c].ongoing_dma_tx_operation =
false;
1319 if (i2c_dma_context[i2c].ongoing_dma_rx_operation ==
false) {
1321 uint32_t data_command =
1322 QM_I2C_IC_DATA_CMD_LSB_MASK &
1323 ((uint8_t *)i2c_dma_context[i2c]
1324 .dma_tx_transfer_config.source_address)
1325 [i2c_dma_context[i2c]
1326 .dma_tx_transfer_config.block_size];
1333 if (((transfer->
stop ==
true) &&
1334 (transfer->
rx_len == 0)) ||
1335 (len != transfer->
tx_len - 1)) {
1337 QM_I2C_IC_DATA_CMD_STOP_BIT_CTRL;
1341 while (!(QM_I2C[i2c]->ic_status & QM_I2C_IC_STATUS_TNF))
1344 QM_I2C[i2c]->ic_data_cmd = data_command;
1352 if ((transfer->
rx_len > 0) &&
1353 (len == transfer->
tx_len)) {
1354 i2c_start_dma_read(i2c);
1360 if ((transfer->
stop ==
true) ||
1361 (len != transfer->
tx_len)) {
1369 while (!(QM_I2C[i2c]->ic_status &
1370 QM_I2C_IC_STATUS_TFE)) {
1372 controller_disable(i2c);
1392 if (error_code == 0) {
1393 error_code = i2c_dma_context[i2c].i2c_error_code;
1396 i2c_dma_transfer_error_callback(i2c, error_code, len);
1403 static void i2c_dma_receive_callback(
void *callback_context, uint32_t len,
1408 qm_i2c_t i2c = ((i2c_dma_context_t *)callback_context)->i2c;
1411 if ((error_code == 0) && (i2c_dma_context[i2c].i2c_error_code == 0)) {
1413 QM_I2C[i2c]->ic_dma_cr &= ~QM_I2C_IC_DMA_CR_RX_ENABLE;
1414 i2c_dma_context[i2c].ongoing_dma_rx_operation =
false;
1417 if (transfer->
stop ==
true) {
1418 controller_disable(i2c);
1432 if (error_code != 0) {
1433 i2c_dma_transfer_error_callback(i2c, error_code, len);
1444 static int i2c_start_dma_read(
const qm_i2c_t i2c)
1449 QM_I2C[i2c]->ic_dma_cr =
1450 QM_I2C_IC_DMA_CR_RX_ENABLE | QM_I2C_IC_DMA_CR_TX_ENABLE;
1453 controller_enable(i2c);
1456 i2c_dma_context[i2c].ongoing_dma_rx_operation =
true;
1457 i2c_dma_context[i2c].ongoing_dma_tx_operation =
true;
1460 i2c_dma_context[i2c].dma_controller_id,
1461 i2c_dma_context[i2c].dma_tx_channel_id,
1462 &(i2c_dma_context[i2c].dma_cmd_transfer_config));
1466 i2c_dma_context[i2c].dma_controller_id,
1467 i2c_dma_context[i2c].dma_rx_channel_id,
1468 &(i2c_dma_context[i2c].dma_rx_transfer_config));
1472 i2c_dma_context[i2c].dma_controller_id,
1473 i2c_dma_context[i2c].dma_tx_channel_id);
1476 i2c_dma_context[i2c].dma_controller_id,
1477 i2c_dma_context[i2c].dma_rx_channel_id);
1499 QM_CHECK(i2c < QM_I2C_NUM, -EINVAL);
1501 QM_CHECK(dma_controller_id <
QM_DMA_NUM, -EINVAL);
1507 i2c_dma_interfaces[i2c][direction];
1521 i2c_dma_context[i2c].dma_rx_channel_id = channel_id;
1523 i2c_dma_context[i2c].dma_tx_channel_id = channel_id;
1525 i2c_dma_context[i2c].dma_controller_id = dma_controller_id;
1526 i2c_dma_context[i2c].i2c = i2c;
1531 &dma_channel_config);
1544 const uint16_t slave_addr)
1549 QM_CHECK(i2c < QM_I2C_NUM, -EINVAL);
1550 QM_CHECK(NULL != xfer, -EINVAL);
1551 QM_CHECK(0 < xfer->
tx_len ? xfer->
tx != NULL : 1, -EINVAL);
1552 QM_CHECK(0 < xfer->
rx_len ? xfer->
rx != NULL : 1, -EINVAL);
1553 QM_CHECK(0 == xfer->
rx_len ? xfer->
tx_len != 0 : 1, -EINVAL);
1554 QM_CHECK(slave_addr <= QM_I2C_IC_TAR_MASK, -EINVAL);
1557 QM_I2C[i2c]->ic_intr_mask = QM_I2C_IC_INTR_MASK_TX_ABORT;
1560 QM_I2C[i2c]->ic_tar &= ~QM_I2C_IC_TAR_MASK;
1561 QM_I2C[i2c]->ic_tar |= slave_addr;
1563 i2c_read_cmd_send[i2c] = xfer->
rx_len;
1564 i2c_transfer[i2c] = xfer;
1567 QM_I2C[i2c]->ic_dma_tdlr = (QM_I2C_FIFO_SIZE / 8);
1570 QM_I2C[i2c]->ic_dma_rdlr = (QM_I2C_FIFO_SIZE / 2) - 1;
1572 i2c_dma_context[i2c].i2c_error_code = 0;
1576 i2c_dma_context[i2c].dma_rx_transfer_config.block_size =
1578 i2c_dma_context[i2c].dma_rx_transfer_config.source_address =
1579 (uint32_t *)&(QM_I2C[i2c]->ic_data_cmd);
1580 i2c_dma_context[i2c]
1581 .dma_rx_transfer_config.destination_address =
1582 (uint32_t *)(xfer->
rx);
1588 i2c_dma_context[i2c].dma_cmd_transfer_config.block_size =
1590 i2c_dma_context[i2c].dma_cmd_transfer_config.source_address =
1591 (uint32_t *)(xfer->
rx);
1600 i < i2c_dma_context[i2c].dma_cmd_transfer_config.block_size;
1602 ((uint8_t *)xfer->
rx)[i] =
1603 DATA_COMMAND_READ_COMMAND_BYTE;
1610 ->rx)[(i2c_dma_context[i2c]
1611 .dma_cmd_transfer_config.block_size -
1612 1)] |= DATA_COMMAND_STOP_BIT_BYTE;
1615 i2c_dma_context[i2c]
1616 .dma_cmd_transfer_config.destination_address =
1617 (uint32_t *)(((uint32_t) & (QM_I2C[i2c]->ic_data_cmd)) + 1);
1625 rc = i2c_start_dma_read(i2c);
1635 i2c_dma_context[i2c].dma_tx_transfer_config.block_size =
1637 i2c_dma_context[i2c].dma_tx_transfer_config.source_address =
1638 (uint32_t *)xfer->
tx;
1639 i2c_dma_context[i2c]
1640 .dma_tx_transfer_config.destination_address =
1641 (uint32_t *)&(QM_I2C[i2c]->ic_data_cmd);
1644 QM_I2C[i2c]->ic_dma_cr = QM_I2C_IC_DMA_CR_TX_ENABLE;
1647 controller_enable(i2c);
1651 i2c_dma_context[i2c].dma_controller_id,
1652 i2c_dma_context[i2c].dma_tx_channel_id,
1653 &(i2c_dma_context[i2c].dma_tx_transfer_config));
1656 i2c_dma_context[i2c].ongoing_dma_rx_operation =
false;
1657 i2c_dma_context[i2c].ongoing_dma_tx_operation =
true;
1659 i2c_dma_context[i2c].dma_controller_id,
1660 i2c_dma_context[i2c].dma_tx_channel_id);
1667 #if (ENABLE_RESTORE_CONTEXT)
1670 QM_CHECK(i2c < QM_I2C_NUM, -EINVAL);
1671 QM_CHECK(ctx != NULL, -EINVAL);
1693 QM_CHECK(i2c < QM_I2C_NUM, -EINVAL);
1694 QM_CHECK(ctx != NULL, -EINVAL);
int qm_i2c_master_dma_transfer(const qm_i2c_t i2c, qm_i2c_transfer_t *const xfer, const uint16_t slave_addr)
Perform a DMA based master transfer on the I2C bus.
QM_RW uint32_t ic_fs_spklen
SS and FS Spike Suppression Limit.
QM_RW uint32_t ic_status
Status.
int qm_i2c_save_context(const qm_i2c_t i2c, qm_i2c_context_t *const ctx)
Save I2C context.
uint32_t tx_len
Write data length.
qm_i2c_speed_t speed
Standard, fast or fast plus mode.
DMA channel configuration structure.
int qm_i2c_master_write(const qm_i2c_t i2c, const uint16_t slave_addr, const uint8_t *const data, uint32_t len, const bool stop, qm_i2c_status_t *const status)
Master write on I2C.
qm_dma_transfer_type_t transfer_type
DMA transfer type.
QM_RW uint32_t ic_intr_stat
Interrupt Status.
int qm_i2c_master_read(const qm_i2c_t i2c, const uint16_t slave_addr, uint8_t *const data, uint32_t len, const bool stop, qm_i2c_status_t *const status)
Master read of I2C.
int qm_i2c_set_config(const qm_i2c_t i2c, const qm_i2c_config_t *const cfg)
Set I2C configuration.
int qm_i2c_set_speed(const qm_i2c_t i2c, const qm_i2c_speed_t speed, const uint16_t lo_cnt, const uint16_t hi_cnt)
Set I2C speed.
QM_RW uint32_t ic_clr_intr
Clear Combined and Individual Interrupt.
Burst length 8 data items.
QM_RW uint32_t ic_clr_rx_under
Clear RX_UNDER Interrupt.
QM_RW uint32_t ic_clr_rx_over
Clear RX_OVER Interrupt.
uint32_t tx_tl
Receive FIFO threshold register.
uint32_t fs_scl_hcnt
Fast Speed Clock SCL High Count.
void * callback_data
User callback data.
QM_RW uint32_t ic_ss_scl_lcnt
Standard Speed Clock SCL Low Count.
uint32_t get_i2c_clk_freq_in_mhz(void)
Get I2C clock frequency in MHz.
uint32_t con
Control Register.
QM_RW uint32_t ic_enable
Enable.
DMA single block transfer configuration structure.
QM_RW uint32_t ic_clr_rx_done
Clear RX_DONE Interrupt.
qm_dma_burst_length_t source_burst_length
DMA source burst length.
QM_RW uint32_t ic_tx_tl
Transmit FIFO Threshold Level.
qm_i2c_slave_stop_t stop_detect_behaviour
Slave stop detect behaviour.
QM_RW uint32_t ic_fs_scl_lcnt
Fast Speed I2C Clock SCL Low Count.
QM_RW uint32_t ic_clr_tx_abrt
Clear TX_ABRT Interrupt.
QM_RW uint32_t ic_data_cmd
Data Buffer and Command.
QM_RW uint32_t ic_clr_stop_det
Clear STOP_DET Interrupt.
void * callback_context
DMA client context passed to the callbacks.
int qm_i2c_dma_channel_config(const qm_i2c_t i2c, const qm_dma_t dma_controller_id, const qm_dma_channel_id_t channel_id, const qm_dma_channel_direction_t direction)
Configure a DMA channel with a specific transfer direction.
bool stop
Master: Generate STOP.
Transfer width of 8 bits.
uint32_t fs_scl_lcnt
Fast Speed I2C Clock SCL Low Count.
int qm_i2c_irq_transfer_terminate(const qm_i2c_t i2c)
Terminate I2C IRQ transfer.
uint16_t slave_addr
I2C address when in slave mode.
QM_RW uint32_t ic_rxflr
Receive FIFO Level.
QM_RW uint32_t ic_clr_tx_over
Clear TX_OVER Interrupt.
QM_RW uint32_t ic_raw_intr_stat
Raw Interrupt Status.
qm_dma_handshake_interface_t handshake_interface
DMA channel handshake interface ID.
qm_i2c_status_t
I2C status type.
int qm_dma_transfer_set_config(const qm_dma_t dma, const qm_dma_channel_id_t channel_id, qm_dma_transfer_t *const transfer_config)
Setup a DMA single block transfer.
int qm_i2c_master_irq_transfer(const qm_i2c_t i2c, const qm_i2c_transfer_t *const xfer, const uint16_t slave_addr)
Interrupt based master transfer on I2C.
qm_i2c_speed_t
QM I2C speed type.
int qm_i2c_get_status(const qm_i2c_t i2c, qm_i2c_status_t *const status)
Retrieve I2C bus status.
int qm_i2c_slave_irq_transfer(const qm_i2c_t i2c, volatile const qm_i2c_transfer_t *const xfer)
Interrupt based slave transfer on I2C.
qm_dma_handshake_polarity_t handshake_polarity
DMA channel handshake polarity.
Start or restart detected.
QM_RW uint32_t ic_fs_scl_hcnt
Fast Speed Clock SCL High Count.
qm_i2c_mode_t mode
Master or slave mode.
QM_RW uint32_t ic_clr_start_det
Clear START_DET Interrupt.
Peripheral to memory transfer.
qm_dma_burst_length_t destination_burst_length
DMA destination burst length.
void clk_sys_udelay(uint32_t microseconds)
Idle loop the processor for at least the value given in microseconds.
qm_dma_transfer_width_t destination_transfer_width
DMA destination transfer width.
int qm_dma_channel_set_config(const qm_dma_t dma, const qm_dma_channel_id_t channel_id, qm_dma_channel_config_t *const channel_config)
Setup a DMA channel configuration.
QM_RW uint32_t ic_ss_scl_hcnt
Standard Speed Clock SCL High Count.
Burst length 4 data items.
int qm_i2c_slave_irq_transfer_update(const qm_i2c_t i2c, volatile const qm_i2c_transfer_t *const xfer)
I2C interrupt based slave transfer buffer update.
uint32_t ss_scl_lcnt
Standard Speed Clock SCL Low Count.
uint32_t ss_scl_hcnt
Standard Speed Clock SCL High Count.
QM_RW uint32_t ic_sar
Slave Address.
Number of DMA controllers.
qm_dma_transfer_width_t source_transfer_width
DMA source transfer width.
int qm_dma_transfer_terminate(const qm_dma_t dma, const qm_dma_channel_id_t channel_id)
Terminate a DMA transfer.
qm_dma_channel_direction_t
DMA channel direction.
uint32_t ic_intr_mask
I2C Interrupt Mask.
QM_RW uint32_t ic_clr_gen_call
Clear GEN_CALL Interrupt.
void(* callback)(void *data, int rc, qm_i2c_status_t status, uint32_t len)
Transfer callback.
int qm_dma_transfer_start(const qm_dma_t dma, const qm_dma_channel_id_t channel_id)
Start a DMA transfer.
uint32_t rx_len
Read buffer length.
Trigger interrupt only if this slave is being addressed.
QM_RW uint32_t ic_intr_mask
Interrupt Mask.
qm_i2c_t
Number of I2C controllers.
Memory to peripheral transfer.
qm_i2c_reg_t * qm_i2c[QM_I2C_NUM]
I2C register block.
QM_RW uint32_t ic_tx_abrt_source
Transmit Abort Source.
I2C context to be saved between sleep/resume.
Standard mode (100 Kbps).
QM_ISR_DECLARE(qm_i2c_0_irq_isr)
ISR for I2C 0 irq mode transfer interrupt.
int qm_i2c_dma_transfer_terminate(const qm_i2c_t i2c)
Terminate any DMA transfer going on on the controller.
uint32_t fs_spklen
SS and FS Spike Suppression Limit.
qm_dma_channel_id_t
DMA channel IDs.
qm_dma_handshake_interface_t
DMA hardware handshake interfaces.
QM_RW uint32_t ic_enable_status
Enable Status.
int qm_i2c_restore_context(const qm_i2c_t i2c, const qm_i2c_context_t *const ctx)
Restore I2C context.
QM_RW uint32_t ic_con
Control Register.
QM_RW uint32_t ic_tar
Master Target Address.
qm_dma_channel_direction_t channel_direction
DMA channel direction.
uint32_t sar
Slave Address.
QM_RW uint32_t ic_rx_tl
Receive FIFO Threshold Level.
QM_RW uint32_t ic_txflr
Transmit FIFO Level.
qm_i2c_addr_t address_mode
7 bit or 10 bit addressing.
QM_RW uint32_t ic_clr_rd_req
Clear RD_REQ Interrupt.
void(* client_callback)(void *callback_context, uint32_t len, int error_code)
Client callback for DMA transfer ISR.