16 static __inline__
bool qm_flash_check_otp_locked(
const uint32_t flash_stts)
19 (QM_FLASH_STTS_ROM_PROG == (flash_stts & QM_FLASH_STTS_ROM_PROG)));
24 QM_CHECK(flash < QM_FLASH_NUM, -EINVAL);
25 QM_CHECK(cfg != NULL, -EINVAL);
26 QM_CHECK(cfg->
wait_states <= QM_FLASH_MAX_WAIT_STATES, -EINVAL);
27 QM_CHECK(cfg->
us_count <= QM_FLASH_MAX_US_COUNT, -EINVAL);
33 (controller->
tmg_ctrl & QM_FLASH_TMG_DEF_MASK) |
37 controller->
ctrl |= QM_FLASH_WRITE_DISABLE_VAL;
44 uint32_t f_addr,
const uint32_t data)
46 QM_CHECK(flash < QM_FLASH_NUM, -EINVAL);
48 QM_CHECK(f_addr < QM_FLASH_MAX_ADDR, -EINVAL);
50 volatile uint32_t *p_wr_data, *p_wr_ctrl;
64 f_addr += QM_FLASH_REGION_DATA_0_SIZE;
77 if (qm_flash_check_otp_locked(controller->
flash_stts)) {
90 f_addr <<= WR_ADDR_OFFSET;
93 *p_wr_ctrl = f_addr |= WR_REQ;
101 uint32_t page_num,
const uint32_t *
const data,
104 QM_CHECK(flash < QM_FLASH_NUM, -EINVAL);
106 QM_CHECK(page_num <= QM_FLASH_MAX_PAGE_NUM, -EINVAL);
107 QM_CHECK(data != NULL, -EINVAL);
108 QM_CHECK(len <= QM_FLASH_PAGE_SIZE_DWORDS, -EINVAL);
111 volatile uint32_t *p_wr_data, *p_wr_ctrl;
122 page_num += QM_FLASH_REGION_DATA_0_PAGES;
133 if (qm_flash_check_otp_locked(controller->
flash_stts)) {
146 page_num <<= (QM_FLASH_PAGE_SIZE_BITS + WR_ADDR_OFFSET);
149 *p_wr_ctrl = page_num | ER_REQ;
156 for (i = 0; i < len; i++) {
157 *p_wr_data = data[i];
158 *p_wr_ctrl = page_num;
159 *p_wr_ctrl |= WR_REQ;
160 page_num += QM_FLASH_ADDR_INC;
169 uint32_t f_addr, uint32_t *
const page_buffer,
170 const uint32_t *
const data_buffer, uint32_t len)
172 QM_CHECK(flash < QM_FLASH_NUM, -EINVAL);
174 QM_CHECK(f_addr < QM_FLASH_MAX_ADDR, -EINVAL);
175 QM_CHECK(page_buffer != NULL, -EINVAL);
176 QM_CHECK(data_buffer != NULL, -EINVAL);
177 QM_CHECK(len <= QM_FLASH_PAGE_SIZE_DWORDS, -EINVAL);
180 volatile uint32_t *p_flash = NULL, *p_wr_data, *p_wr_ctrl;
193 p_flash = (uint32_t *)(QM_FLASH_REGION_SYS_0_BASE +
194 (f_addr & QM_FLASH_PAGE_MASK));
196 f_addr += QM_FLASH_REGION_DATA_0_SIZE;
198 if (flash == QM_FLASH_0) {
199 p_flash = (uint32_t *)(QM_FLASH_REGION_SYS_0_BASE +
200 (f_addr & QM_FLASH_PAGE_MASK));
202 p_flash = (uint32_t *)(QM_FLASH_REGION_SYS_1_BASE +
203 (f_addr & QM_FLASH_PAGE_MASK));
206 #error("Unsupported / unspecified processor type")
214 p_flash = (uint32_t *)(QM_FLASH_REGION_DATA_0_BASE +
215 (f_addr & QM_FLASH_PAGE_MASK));
222 if (qm_flash_check_otp_locked(controller->
flash_stts)) {
228 p_flash = (uint32_t *)(QM_FLASH_REGION_OTP_0_BASE +
229 (f_addr & QM_FLASH_PAGE_MASK));
238 for (i = 0; i < QM_FLASH_PAGE_SIZE_DWORDS; i++) {
239 page_buffer[i] = *p_flash;
244 *p_wr_ctrl = ((f_addr & QM_FLASH_PAGE_MASK) << WR_ADDR_OFFSET) | ER_REQ;
247 j = (f_addr & QM_FLASH_ADDRESS_MASK) >> 2;
248 for (i = 0; i < len; i++, j++) {
249 page_buffer[j] = data_buffer[i];
257 f_addr &= QM_FLASH_PAGE_MASK;
258 f_addr <<= WR_ADDR_OFFSET;
260 for (i = 0; i < QM_FLASH_PAGE_SIZE_DWORDS; i++) {
261 *p_wr_data = page_buffer[i];
262 *p_wr_ctrl = f_addr |= WR_REQ;
263 f_addr += QM_FLASH_ADDR_INC;
274 QM_CHECK(flash < QM_FLASH_NUM, -EINVAL);
276 QM_CHECK(page_num <= QM_FLASH_MAX_PAGE_NUM, -EINVAL);
284 page_num += QM_FLASH_REGION_DATA_0_PAGES;
289 (page_num << (QM_FLASH_PAGE_SIZE_BITS + WR_ADDR_OFFSET)) |
296 if (qm_flash_check_otp_locked(controller->
flash_stts)) {
301 (page_num << (QM_FLASH_PAGE_SIZE_BITS + WR_ADDR_OFFSET)) |
316 QM_CHECK(flash < QM_FLASH_NUM, -EINVAL);
324 if (qm_flash_check_otp_locked(controller->
flash_stts)) {
328 controller->
ctrl |= MASS_ERASE_INFO;
330 controller->
ctrl |= MASS_ERASE;
336 #if (ENABLE_RESTORE_CONTEXT)
339 QM_CHECK(flash < QM_FLASH_NUM, -EINVAL);
340 QM_CHECK(ctx != NULL, -EINVAL);
353 QM_CHECK(flash < QM_FLASH_NUM, -EINVAL);
354 QM_CHECK(ctx != NULL, -EINVAL);
QM_RW uint32_t flash_stts
FLASH_STTS.
int qm_flash_restore_context(const qm_flash_t flash, const qm_flash_context_t *const ctx)
Restore flash context.
int qm_flash_page_update(const qm_flash_t flash, const qm_flash_region_t region, uint32_t f_addr, uint32_t *const page_buffer, const uint32_t *const data_buffer, uint32_t len)
Write multiple of 4 bytes of data to Flash.
uint32_t ctrl
Control Register.
Total number of flash regions.
uint32_t tmg_ctrl
Flash Timing Control Register.
qm_flash_t
Number of Flash controllers.
int qm_flash_mass_erase(const qm_flash_t flash, const uint8_t include_rom)
Perform mass erase.
QM_RW uint32_t flash_wr_ctrl
FLASH_WR_CTRL.
qm_flash_disable_t write_disable
Write Disable.
int qm_flash_save_context(const qm_flash_t flash, qm_flash_context_t *const ctx)
Save flash context.
Flash Data region (Quark D2000 only).
QM_RW uint32_t tmg_ctrl
TMG_CTRL.
int qm_flash_word_write(const qm_flash_t flash, const qm_flash_region_t region, uint32_t f_addr, const uint32_t data)
Write 4 bytes of data to Flash.
QM_RW uint32_t rom_wr_data
ROM_WR_DATA.
QM_RW uint32_t rom_wr_ctrl
ROM_WR_CTRL.
qm_flash_region_t
Flash region enum.
QM_RW uint32_t flash_wr_data
FLASH_WR_DATA.
uint8_t us_count
Number of clocks in a microsecond.
Flash configuration structure.
uint8_t wait_states
Read wait state.
int qm_flash_page_erase(const qm_flash_t flash, const qm_flash_region_t region, uint32_t page_num)
Erase one page of Flash.
int qm_flash_page_write(const qm_flash_t flash, const qm_flash_region_t region, uint32_t page_num, const uint32_t *const data, uint32_t len)
Write a flash page.
int qm_flash_set_config(const qm_flash_t flash, const qm_flash_config_t *cfg)
Configure a Flash controller.