Intel® Quark™ Microcontroller Software Interface  1.4.0
Intel® Quark™ Microcontroller BSP
qm_pinmux.c
1 /*
2  * {% copyright %}
3  */
4 
5 #include "qm_pinmux.h"
6 #include "qm_common.h"
7 
8 #define MASK_1BIT (0x1)
9 #define MASK_2BIT (0x3)
10 
11 /**
12  * Calculate the register index for a specific pin.
13  *
14  * @param[in] pin The pin to be used.
15  * @param[in] width The width in bits for each pin in the register.
16  *
17  * @return The register index of the given pin.
18  */
19 static uint32_t pin_to_register(uint32_t pin, uint32_t width)
20 {
21  return (pin / (32 / width));
22 }
23 
24 /**
25  * Calculate the offset for a pin within a register.
26  *
27  * @param[in] pin The pin to be used.
28  * @param[in] width The width in bits for each pin in the register.
29  *
30  * @return The offset for the pin within the register.
31  */
32 static uint32_t pin_to_offset(uint32_t pin, uint32_t width)
33 {
34  return ((pin % (32 / width)) * width);
35 }
36 
37 int qm_pmux_select(const qm_pin_id_t pin, const qm_pmux_fn_t fn)
38 {
39  QM_CHECK(pin < QM_PIN_ID_NUM, -EINVAL);
40  QM_CHECK(fn <= QM_PMUX_FN_3, -EINVAL);
41 
42  uint32_t reg = pin_to_register(pin, 2);
43  uint32_t offs = pin_to_offset(pin, 2);
44 
45  QM_SCSS_PMUX->pmux_sel[reg] &= ~(MASK_2BIT << offs);
46  QM_SCSS_PMUX->pmux_sel[reg] |= (fn << offs);
47 
48  return 0;
49 }
50 
51 int qm_pmux_set_slew(const qm_pin_id_t pin, const qm_pmux_slew_t slew)
52 {
53  QM_CHECK(pin < QM_PIN_ID_NUM, -EINVAL);
54  QM_CHECK(slew < QM_PMUX_SLEW_NUM, -EINVAL);
55 
56  uint32_t reg = pin_to_register(pin, 1);
57  uint32_t mask = MASK_1BIT << pin_to_offset(pin, 1);
58 
59  if (slew == 0) {
60  QM_SCSS_PMUX->pmux_slew[reg] &= ~mask;
61  } else {
62  QM_SCSS_PMUX->pmux_slew[reg] |= mask;
63  }
64  return 0;
65 }
66 
67 int qm_pmux_input_en(const qm_pin_id_t pin, const bool enable)
68 {
69  QM_CHECK(pin < QM_PIN_ID_NUM, -EINVAL);
70 
71  uint32_t reg = pin_to_register(pin, 1);
72  uint32_t mask = MASK_1BIT << pin_to_offset(pin, 1);
73 
74  if (enable == false) {
75  QM_SCSS_PMUX->pmux_in_en[reg] &= ~mask;
76  } else {
77  QM_SCSS_PMUX->pmux_in_en[reg] |= mask;
78  }
79  return 0;
80 }
81 
82 int qm_pmux_pullup_en(const qm_pin_id_t pin, const bool enable)
83 {
84  QM_CHECK(pin < QM_PIN_ID_NUM, -EINVAL);
85 
86  uint32_t reg = pin_to_register(pin, 1);
87  uint32_t mask = MASK_1BIT << pin_to_offset(pin, 1);
88 
89  if (enable == false) {
90  QM_SCSS_PMUX->pmux_pullup[reg] &= ~mask;
91  } else {
92  QM_SCSS_PMUX->pmux_pullup[reg] |= mask;
93  }
94  return 0;
95 }
qm_pin_id_t
External Pad pin identifiers.
Definition: qm_pinmux.h:45
Max number of slew rate options.
Definition: qm_pinmux.h:39
int qm_pmux_input_en(const qm_pin_id_t pin, const bool enable)
Enable input for a pin in the pin mux controller.
Definition: qm_pinmux.c:67
qm_pmux_slew_t
Pin slew rate setting.
Definition: qm_pinmux.h:31
Gpio function 0.
Definition: qm_pinmux.h:25
int qm_pmux_select(const qm_pin_id_t pin, const qm_pmux_fn_t fn)
Set up pin muxing for a SoC pin.
Definition: qm_pinmux.c:37
int qm_pmux_set_slew(const qm_pin_id_t pin, const qm_pmux_slew_t slew)
Set up pin's slew rate in the pin mux controller.
Definition: qm_pinmux.c:51
int qm_pmux_pullup_en(const qm_pin_id_t pin, const bool enable)
Enable pullup for a pin in the pin mux controller.
Definition: qm_pinmux.c:82
qm_pmux_fn_t
Pin function type.
Definition: qm_pinmux.h:21