Intel® Quark™ Microcontroller Software Interface  1.4.0
Intel® Quark™ Microcontroller BSP
qm_interrupt_router.c
1 /*
2  * {% copyright %}
3  */
4 
5 #include "qm_common.h"
6 #include "qm_soc_regs.h"
7 #include "qm_interrupt_router.h"
8 #include "qm_interrupt_router_regs.h"
9 
10 /* Event router base addr for LMT interrupt routing, for linear IRQ mapping */
11 #define INTERRUPT_ROUTER_LMT_INT_MASK_BASE \
12  (&QM_INTERRUPT_ROUTER->i2c_master_0_int_mask)
13 
14 void _qm_ir_unmask_int(uint32_t irq, uint32_t register_offset)
15 {
16  uint32_t *interrupt_router_intmask;
17 
18  /* Route peripheral interrupt to Lakemont/Sensor Subsystem */
19  interrupt_router_intmask =
20  (uint32_t *)INTERRUPT_ROUTER_LMT_INT_MASK_BASE + register_offset;
21 
22  if (!QM_IR_INT_LOCK_MASK(*interrupt_router_intmask)) {
23  switch (irq) {
24  case QM_IRQ_COMPARATOR_0_INT:
25  /*
26  * Comparator error mask uses 1 bit per Comparator
27  * rather than the generic host mask.
28  */
29  QM_INTERRUPT_ROUTER->comparator_0_host_int_mask &=
30  ~0x0007ffff;
31  break;
32  case QM_IRQ_DMA_0_ERROR_INT:
33  /*
34  * DMA error mask uses 1 bit per DMA channel rather than
35  * the
36  * generic host mask.
37  */
38  *interrupt_router_intmask &= ~QM_IR_DMA_ERROR_HOST_MASK;
39  break;
40  default:
41  QM_IR_UNMASK_INTERRUPTS(*interrupt_router_intmask);
42  break;
43  }
44  }
45 }
46 
47 void _qm_ir_mask_int(uint32_t irq, uint32_t register_offset)
48 {
49  uint32_t *interrupt_router_intmask;
50 
51  /* Route peripheral interrupt to Lakemont/Sensor Subsystem */
52  interrupt_router_intmask =
53  (uint32_t *)INTERRUPT_ROUTER_LMT_INT_MASK_BASE + register_offset;
54 
55  /**/
56  if (!QM_IR_INT_LOCK_MASK(*interrupt_router_intmask)) {
57  switch (irq) {
58  case QM_IRQ_COMPARATOR_0_INT:
59  QM_INTERRUPT_ROUTER->comparator_0_host_int_mask |=
60  0x0007ffff;
61  break;
62  case QM_IRQ_DMA_0_ERROR_INT:
63  /*
64  * DMA error mask uses 1 bit per DMA channel rather than
65  * the
66  * generic host mask.
67  */
68  *interrupt_router_intmask |= QM_IR_DMA_ERROR_HOST_MASK;
69  break;
70  default:
71  QM_IR_MASK_INTERRUPTS(*interrupt_router_intmask);
72  break;
73  }
74  }
75 }