6 #include "qm_mailbox.h"
7 #include "qm_interrupt.h"
8 #include "qm_interrupt_router.h"
18 #if HAS_MAILBOX_SMM_DEST
19 #define MBOX_CHECK_IF_ACTIVE_AGENT_MBOX_ACTIVE_AGENT_IS_SMM \
20 (QM_LAKEMONT && QM_SMM)
22 #define MBOX_CHECK_IF_ACTIVE_AGENT_MBOX_ACTIVE_AGENT_IS_SMM (0)
25 #if HAS_MAILBOX_LAKEMONT_DEST
26 #if MBOX_CHECK_IF_ACTIVE_AGENT_MBOX_ACTIVE_AGENT_IS_SMM
27 #define MBOX_ACTIVE_AGENT_IS_SMM (1)
28 #define ACTIVE_CORE_DEST QM_MBOX_TO_SMM
29 #define MBOX_ACTIVE_CORE_ALL_INT_MASK QM_IR_MBOX_SMI_ALL_INT_MASK
30 #define MBOX_INT_LOCK_MASK(N) QM_IR_MBOX_SMI_INT_LOCK_MASK(N)
32 #define MBOX_INT_LOCK_HALT_MASK(N)
33 #define MBOX_IS_INT_MASK_EN(N) QM_IR_MBOX_IS_SMI_INT_MASK_EN(N)
34 #define MBOX_ENABLE_INT_MASK(N) QM_IR_MBOX_ENABLE_SMM_INT_MASK(N)
35 #define MBOX_DISABLE_INT_MASK(N) QM_IR_MBOX_DISABLE_SMM_INT_MASK(N)
37 #define MBOX_ACTIVE_AGENT_IS_SMM (0)
38 #define ACTIVE_CORE_DEST QM_MBOX_TO_LMT
39 #define MBOX_ACTIVE_CORE_ALL_INT_MASK QM_IR_MBOX_LMT_ALL_INT_MASK
40 #define MBOX_INT_LOCK_MASK(N) QM_IR_MBOX_LMT_INT_LOCK_MASK(N)
41 #define MBOX_INT_LOCK_HALT_MASK(N) QM_IR_MBOX_LMT_INT_LOCK_HALT_MASK(N)
42 #define MBOX_IS_INT_MASK_EN(N) QM_IR_MBOX_IS_LMT_INT_MASK_EN(N)
43 #define MBOX_ENABLE_INT_MASK(N) QM_IR_MBOX_ENABLE_LMT_INT_MASK(N)
44 #define MBOX_DISABLE_INT_MASK(N) QM_IR_MBOX_DISABLE_LMT_INT_MASK(N)
48 #if HAS_MAILBOX_SENSOR_SUB_SYSTEM_DEST
50 #define MBOX_ACTIVE_AGENT_IS_SMM (0)
51 #define ACTIVE_CORE_DEST QM_MBOX_TO_SS
52 #define MBOX_ACTIVE_CORE_ALL_INT_MASK QM_IR_MBOX_SS_ALL_INT_MASK
53 #define MBOX_INT_LOCK_MASK(N) QM_IR_MBOX_SS_INT_LOCK_HALT_MASK(N)
54 #define MBOX_INT_LOCK_HALT_MASK(N) QM_IR_MBOX_SS_INT_LOCK_MASK(N)
55 #define MBOX_IS_INT_MASK_EN(N) QM_IR_MBOX_IS_SS_INT_MASK_EN(N)
56 #define MBOX_ENABLE_INT_MASK(N) QM_IR_MBOX_ENABLE_SS_INT_MASK(N)
57 #define MBOX_DISABLE_INT_MASK(N) QM_IR_MBOX_DISABLE_SS_INT_MASK(N)
61 #if HAS_MAILBOX_BLUETOOTH_SUB_SYSTEM_DEST
63 #define MBOX_ACTIVE_AGENT_IS_SMM (0)
64 #define ACTIVE_CORE_DEST QM_MBOX_TO_BLE
65 #define MBOX_ALL_INT_MASK QM_MBOX_BLE_ALL_INT_MASK
72 #define MBOX_INT_LOCK_MASK(N) (true)
73 #define MBOX_INT_LOCK_HALT_MASK(N) (true)
78 #define MBOX_IS_INT_MASK_EN(N) (true)
79 #define MBOX_ENABLE_INT_MASK(N) QM_IR_MBOX_ENABLE_BLE_INT_MASK(N)
80 #define MBOX_DISABLE_INT_MASK(N) QM_IR_MBOX_DISABLE_BLE_INT_MASK(N)
84 #if MBOX_ACTIVE_AGENT_IS_SMM
89 #define MBOX_CHECK_DESTINATION(_dest) (true)
96 #define MBOX_CHECK_POLLING_MODE(_dest) (true)
98 #define MBOX_CHECK_DESTINATION(_dest) (ACTIVE_CORE_DEST == (_dest))
99 #define MBOX_CHECK_POLLING_MODE(_mode) (QM_MBOX_POLLING_MODE == (_mode))
101 #if (!MBOX_ACTIVE_AGENT_IS_SMM)
103 static void mailbox_isr_handler(
void);
127 static volatile uint32_t active_proc_active_ints = 0;
130 static qm_mailbox_info_t mailbox_devs[NUM_MAILBOXES];
134 mailbox_isr_handler();
135 QM_ISR_EOI(QM_IRQ_MAILBOX_0_INT_VECTOR);
141 static void mailbox_isr_handler(
void)
145 uint32_t chall_int_sts =
146 (QM_MAILBOX->mbox_chan_int_sts & active_proc_active_ints);
148 #if (ACTIVE_CORE_DEST != QM_MBOX_TO_BLE)
159 if (0 == chall_int_sts) {
160 chall_int_sts = (~MBOX_ACTIVE_CORE_ALL_INT_MASK) &
161 (QM_MAILBOX->mbox_chan_int_sts) &
162 (BIT(NUM_MAILBOXES + 1) - 1);
166 for (i = 0; chall_int_sts; i++, chall_int_sts >>= 1) {
167 if ((chall_int_sts & 1) == 0) {
170 if (mbox_reg[i].ch_sts & QM_MBOX_CH_STS_CTRL_INT) {
171 if (NULL != mailbox_devs[i].callback) {
173 mailbox_devs[i].callback(
174 mailbox_devs[i].callback_data);
180 mbox_reg[i].
ch_sts = QM_MBOX_CH_STS_CTRL_INT;
189 QM_CHECK((
QM_MBOX_CH_0 <= mbox_ch) && (mbox_ch < NUM_MAILBOXES),
191 qm_mailbox_info_t *device = &mailbox_devs[mbox_ch];
194 QM_IR_MASK_INT(QM_IRQ_MAILBOX_0_INT);
197 device->dest = config->
dest;
200 if (QM_MBOX_UNUSED != config->
dest) {
203 QM_CHECK(NULL != config->
callback, -EINVAL);
206 device->callback = config->
callback;
208 device->callback_data = config->callback_data;
213 active_proc_active_ints |= BIT(mbox_ch);
221 if (!(MBOX_INT_LOCK_MASK(mbox_ch))) {
224 MBOX_ENABLE_INT_MASK(mbox_ch);
228 QM_CHECK(MBOX_IS_INT_MASK_EN(mbox_ch), -EIO);
237 if (!(MBOX_INT_LOCK_MASK(mbox_ch))) {
240 MBOX_DISABLE_INT_MASK(mbox_ch);
244 device->callback = NULL;
245 device->callback_data = 0;
250 if (!(MBOX_INT_LOCK_MASK(mbox_ch))) {
253 MBOX_DISABLE_INT_MASK(mbox_ch);
259 active_proc_active_ints &= ~(BIT(mbox_ch));
261 device->dest = QM_MBOX_UNUSED;
263 device->callback = NULL;
264 device->callback_data = 0;
268 QM_IR_UNMASK_INT(QM_IRQ_MAILBOX_0_INT);
275 QM_CHECK((
QM_MBOX_CH_0 <= mbox_ch) && (mbox_ch < NUM_MAILBOXES),
277 QM_CHECK(NULL != msg, -EINVAL);
282 status = QM_MAILBOX->mbox[mbox_ch].
ch_sts;
285 if (
false == (status & (QM_MBOX_CH_STS_CTRL_INT | QM_MBOX_CH_STS))) {
292 mbox_reg->
ch_ctrl = msg->
ctrl | QM_MBOX_CH_CTRL_INT;
302 QM_CHECK((
QM_MBOX_CH_0 <= mbox_ch) && (mbox_ch < NUM_MAILBOXES),
304 QM_CHECK(NULL != msg, -EINVAL);
311 if (MBOX_CHECK_DESTINATION(mailbox_devs[mbox_ch].dest)) {
312 status = mbox_reg->
ch_sts;
315 if (status & QM_MBOX_CH_STS) {
318 msg->
ctrl = mbox_reg->
ch_ctrl & (~QM_MBOX_CH_CTRL_INT);
324 if (MBOX_CHECK_POLLING_MODE(
325 mailbox_devs[mbox_ch].mode)) {
330 mbox_reg->
ch_sts = QM_MBOX_CH_STS_CTRL_INT;
336 mbox_reg->
ch_sts = QM_MBOX_CH_STS;
353 QM_CHECK((
QM_MBOX_CH_0 <= mbox_ch) && (mbox_ch < NUM_MAILBOXES),
355 QM_CHECK(NULL != status, -EINVAL);
357 *status = QM_MAILBOX->mbox[mbox_ch].ch_sts;
void(* qm_mbox_callback_t)(void *data)
Definition of the mailbox callback function prototype.
int qm_mbox_ch_read(const qm_mbox_ch_t mbox_ch, qm_mbox_msg_t *const msg)
Read specified mailbox channel.
qm_mbox_ch_t
Mailbox channel identifiers.
QM_RW uint32_t ch_data[4]
Channel Payload Data Word 0.
qm_mbox_destination_t dest
< Mailbox Destination
QM_RW uint32_t ch_ctrl
Channel Control Word.
Mailbox channel operates in polling mode.
uint32_t data[QM_MBOX_PAYLOAD_NUM]
Mailbox data buffer.
int qm_mbox_ch_write(const qm_mbox_ch_t mbox_ch, const qm_mbox_msg_t *const msg)
Write to a specified mailbox channel.
int qm_mbox_ch_get_status(const qm_mbox_ch_t mbox_ch, qm_mbox_ch_status_t *const status)
Retrieve the specified mailbox channel status.
uint32_t ctrl
Control word - bits 30 to 0 used as data/message id, bit 31 triggers channel interrupt when set by th...
Definition of the mailbox message.
QM_ISR_DECLARE(qm_mailbox_0_isr)
ISR for Mailbox interrupt.
QM_RW uint32_t ch_sts
Channel status.
int qm_mbox_ch_set_config(const qm_mbox_ch_t mbox_ch, const qm_mbox_config_t *const config)
Set the mailbox channel configuration.
Mailbox register structure.
qm_mbox_destination_t
Definition of the mailbox direction of operation The direction of communication for each channel is c...
Mailbox channel operates in interrupt mode.
qm_mbox_mode_t mode
Message callback.
qm_mbox_mode_t
Definition of the mailbox mode of operation, interrupt mode or polling mode.
Mailbox Configuration Structure.
qm_mbox_callback_t callback
Callback function data to return via the callback function.
qm_mbox_ch_status_t
Mailbox channel status return codes.