Intel® Quark™ Microcontroller Software Interface  1.4.0
Intel® Quark™ Microcontroller BSP
Clock Management

Clock Management. More...

Enumerations

enum  clk_sys_div_t {
  CLK_SYS_DIV_1, CLK_SYS_DIV_2, CLK_SYS_DIV_4, CLK_SYS_DIV_8,
  CLK_SYS_DIV_16, CLK_SYS_DIV_32, CLK_SYS_DIV_64, CLK_SYS_DIV_128 ,
  CLK_SYS_DIV_1, CLK_SYS_DIV_2, CLK_SYS_DIV_4, CLK_SYS_DIV_8
}
 System clock divider type. More...
 
enum  clk_sys_mode_t {
  CLK_SYS_HYB_OSC_32MHZ = 0, CLK_SYS_HYB_OSC_16MHZ = 1, CLK_SYS_HYB_OSC_8MHZ = 2, CLK_SYS_HYB_OSC_4MHZ = 3,
  CLK_SYS_RTC_OSC = 4, CLK_SYS_CRYSTAL_OSC = 5, CLK_SYS_HYB_OSC_32MHZ = 0, CLK_SYS_HYB_OSC_16MHZ = 1,
  CLK_SYS_HYB_OSC_8MHZ = 2, CLK_SYS_HYB_OSC_4MHZ = 3, CLK_SYS_RTC_OSC = 4, CLK_SYS_CRYSTAL_OSC = 5
}
 System clock mode type. More...
 
enum  clk_periph_div_t {
  CLK_PERIPH_DIV_1, CLK_PERIPH_DIV_2, CLK_PERIPH_DIV_4, CLK_PERIPH_DIV_8,
  CLK_PERIPH_DIV_1, CLK_PERIPH_DIV_2, CLK_PERIPH_DIV_4, CLK_PERIPH_DIV_8
}
 Peripheral clock divider type. More...
 
enum  clk_gpio_db_div_t {
  CLK_GPIO_DB_DIV_1, CLK_GPIO_DB_DIV_2, CLK_GPIO_DB_DIV_4, CLK_GPIO_DB_DIV_8,
  CLK_GPIO_DB_DIV_16, CLK_GPIO_DB_DIV_32, CLK_GPIO_DB_DIV_64, CLK_GPIO_DB_DIV_128,
  CLK_GPIO_DB_DIV_1, CLK_GPIO_DB_DIV_2, CLK_GPIO_DB_DIV_4, CLK_GPIO_DB_DIV_8,
  CLK_GPIO_DB_DIV_16, CLK_GPIO_DB_DIV_32, CLK_GPIO_DB_DIV_64, CLK_GPIO_DB_DIV_128
}
 GPIO clock debounce divider type. More...
 
enum  clk_ext_div_t {
  CLK_EXT_DIV_1, CLK_EXT_DIV_2, CLK_EXT_DIV_4, CLK_EXT_DIV_8,
  CLK_EXT_DIV_1, CLK_EXT_DIV_2, CLK_EXT_DIV_4, CLK_EXT_DIV_8
}
 External crystal clock divider type. More...
 
enum  clk_rtc_div_t {
  CLK_RTC_DIV_1, CLK_RTC_DIV_2, CLK_RTC_DIV_4, CLK_RTC_DIV_8,
  CLK_RTC_DIV_16, CLK_RTC_DIV_32, CLK_RTC_DIV_64, CLK_RTC_DIV_128,
  CLK_RTC_DIV_256, CLK_RTC_DIV_512, CLK_RTC_DIV_1024, CLK_RTC_DIV_2048,
  CLK_RTC_DIV_4096, CLK_RTC_DIV_8192, CLK_RTC_DIV_16384, CLK_RTC_DIV_32768,
  CLK_RTC_DIV_1, CLK_RTC_DIV_2, CLK_RTC_DIV_4, CLK_RTC_DIV_8,
  CLK_RTC_DIV_16, CLK_RTC_DIV_32, CLK_RTC_DIV_64, CLK_RTC_DIV_128,
  CLK_RTC_DIV_256, CLK_RTC_DIV_512, CLK_RTC_DIV_1024, CLK_RTC_DIV_2048,
  CLK_RTC_DIV_4096, CLK_RTC_DIV_8192, CLK_RTC_DIV_16384, CLK_RTC_DIV_32768
}
 RTC clock divider type. More...
 
enum  clk_sys_div_t {
  CLK_SYS_DIV_1, CLK_SYS_DIV_2, CLK_SYS_DIV_4, CLK_SYS_DIV_8,
  CLK_SYS_DIV_16, CLK_SYS_DIV_32, CLK_SYS_DIV_64, CLK_SYS_DIV_128 ,
  CLK_SYS_DIV_1, CLK_SYS_DIV_2, CLK_SYS_DIV_4, CLK_SYS_DIV_8
}
 System clock divider type. More...
 
enum  clk_sys_mode_t {
  CLK_SYS_HYB_OSC_32MHZ = 0, CLK_SYS_HYB_OSC_16MHZ = 1, CLK_SYS_HYB_OSC_8MHZ = 2, CLK_SYS_HYB_OSC_4MHZ = 3,
  CLK_SYS_RTC_OSC = 4, CLK_SYS_CRYSTAL_OSC = 5, CLK_SYS_HYB_OSC_32MHZ = 0, CLK_SYS_HYB_OSC_16MHZ = 1,
  CLK_SYS_HYB_OSC_8MHZ = 2, CLK_SYS_HYB_OSC_4MHZ = 3, CLK_SYS_RTC_OSC = 4, CLK_SYS_CRYSTAL_OSC = 5
}
 System clock mode type. More...
 
enum  clk_periph_div_t {
  CLK_PERIPH_DIV_1, CLK_PERIPH_DIV_2, CLK_PERIPH_DIV_4, CLK_PERIPH_DIV_8,
  CLK_PERIPH_DIV_1, CLK_PERIPH_DIV_2, CLK_PERIPH_DIV_4, CLK_PERIPH_DIV_8
}
 Peripheral clock divider type. More...
 
enum  clk_gpio_db_div_t {
  CLK_GPIO_DB_DIV_1, CLK_GPIO_DB_DIV_2, CLK_GPIO_DB_DIV_4, CLK_GPIO_DB_DIV_8,
  CLK_GPIO_DB_DIV_16, CLK_GPIO_DB_DIV_32, CLK_GPIO_DB_DIV_64, CLK_GPIO_DB_DIV_128,
  CLK_GPIO_DB_DIV_1, CLK_GPIO_DB_DIV_2, CLK_GPIO_DB_DIV_4, CLK_GPIO_DB_DIV_8,
  CLK_GPIO_DB_DIV_16, CLK_GPIO_DB_DIV_32, CLK_GPIO_DB_DIV_64, CLK_GPIO_DB_DIV_128
}
 GPIO clock debounce divider type. More...
 
enum  clk_ext_div_t {
  CLK_EXT_DIV_1, CLK_EXT_DIV_2, CLK_EXT_DIV_4, CLK_EXT_DIV_8,
  CLK_EXT_DIV_1, CLK_EXT_DIV_2, CLK_EXT_DIV_4, CLK_EXT_DIV_8
}
 External crystal clock divider type. More...
 
enum  clk_rtc_div_t {
  CLK_RTC_DIV_1, CLK_RTC_DIV_2, CLK_RTC_DIV_4, CLK_RTC_DIV_8,
  CLK_RTC_DIV_16, CLK_RTC_DIV_32, CLK_RTC_DIV_64, CLK_RTC_DIV_128,
  CLK_RTC_DIV_256, CLK_RTC_DIV_512, CLK_RTC_DIV_1024, CLK_RTC_DIV_2048,
  CLK_RTC_DIV_4096, CLK_RTC_DIV_8192, CLK_RTC_DIV_16384, CLK_RTC_DIV_32768,
  CLK_RTC_DIV_1, CLK_RTC_DIV_2, CLK_RTC_DIV_4, CLK_RTC_DIV_8,
  CLK_RTC_DIV_16, CLK_RTC_DIV_32, CLK_RTC_DIV_64, CLK_RTC_DIV_128,
  CLK_RTC_DIV_256, CLK_RTC_DIV_512, CLK_RTC_DIV_1024, CLK_RTC_DIV_2048,
  CLK_RTC_DIV_4096, CLK_RTC_DIV_8192, CLK_RTC_DIV_16384, CLK_RTC_DIV_32768
}
 RTC clock divider type. More...
 

Functions

int clk_sys_set_mode (const clk_sys_mode_t mode, const clk_sys_div_t div)
 Set clock mode and divisor. More...
 
int clk_trim_read (uint32_t *const value)
 Read the silicon oscillator trim code for the current frequency. More...
 
int clk_trim_apply (const uint32_t value)
 Apply silicon oscillator trim code. More...
 
int clk_adc_set_div (const uint16_t div)
 Change divider value of ADC clock. More...
 
int clk_periph_set_div (const clk_periph_div_t div)
 Change divider value of peripheral clock. More...
 
int clk_gpio_db_set_div (const clk_gpio_db_div_t div)
 Change divider value of GPIO debounce clock. More...
 
int clk_ext_set_div (const clk_ext_div_t div)
 Change divider value of external clock. More...
 
int clk_rtc_set_div (const clk_rtc_div_t div)
 Change divider value of RTC. More...
 
int clk_periph_enable (const clk_periph_t clocks)
 Enable clocks for peripherals / registers. More...
 
int clk_periph_disable (const clk_periph_t clocks)
 Disable clocks for peripherals / registers. More...
 
uint32_t clk_sys_get_ticks_per_us (void)
 Get number of system ticks per micro second. More...
 
void clk_sys_udelay (uint32_t microseconds)
 Idle loop the processor for at least the value given in microseconds. More...
 
int clk_dma_enable (void)
 Enable the DMA clock. More...
 
int clk_dma_disable (void)
 Disable the DMA clock. More...
 
uint32_t get_i2c_clk_freq_in_mhz (void)
 Get I2C clock frequency in MHz. More...
 
int clk_sys_usb_enable (void)
 Enable the USB Clock mode. More...
 
int clk_sys_usb_disable (void)
 Disable the USB Clock mode. More...
 

Detailed Description

Clock Management.

Enumeration Type Documentation

External crystal clock divider type.

Enumerator
CLK_EXT_DIV_1 

External Crystal Clock Divider = 1.

CLK_EXT_DIV_2 

External Crystal Clock Divider = 2.

CLK_EXT_DIV_4 

External Crystal Clock Divider = 4.

CLK_EXT_DIV_8 

External Crystal Clock Divider = 8.

CLK_EXT_DIV_1 

External Crystal Clock Divider = 1.

CLK_EXT_DIV_2 

External Crystal Clock Divider = 2.

CLK_EXT_DIV_4 

External Crystal Clock Divider = 4.

CLK_EXT_DIV_8 

External Crystal Clock Divider = 8.

Definition at line 86 of file clk.h.

External crystal clock divider type.

Enumerator
CLK_EXT_DIV_1 

External Crystal Clock Divider = 1.

CLK_EXT_DIV_2 

External Crystal Clock Divider = 2.

CLK_EXT_DIV_4 

External Crystal Clock Divider = 4.

CLK_EXT_DIV_8 

External Crystal Clock Divider = 8.

CLK_EXT_DIV_1 

External Crystal Clock Divider = 1.

CLK_EXT_DIV_2 

External Crystal Clock Divider = 2.

CLK_EXT_DIV_4 

External Crystal Clock Divider = 4.

CLK_EXT_DIV_8 

External Crystal Clock Divider = 8.

Definition at line 87 of file clk.h.

GPIO clock debounce divider type.

Enumerator
CLK_GPIO_DB_DIV_1 

GPIO Clock Debounce Divider = 1.

CLK_GPIO_DB_DIV_2 

GPIO Clock Debounce Divider = 2.

CLK_GPIO_DB_DIV_4 

GPIO Clock Debounce Divider = 4.

CLK_GPIO_DB_DIV_8 

GPIO Clock Debounce Divider = 8.

CLK_GPIO_DB_DIV_16 

GPIO Clock Debounce Divider = 16.

CLK_GPIO_DB_DIV_32 

GPIO Clock Debounce Divider = 32.

CLK_GPIO_DB_DIV_64 

GPIO Clock Debounce Divider = 64.

CLK_GPIO_DB_DIV_128 

GPIO Clock Debounce Divider = 128.

CLK_GPIO_DB_DIV_1 

GPIO Clock Debounce Divider = 1.

CLK_GPIO_DB_DIV_2 

GPIO Clock Debounce Divider = 2.

CLK_GPIO_DB_DIV_4 

GPIO Clock Debounce Divider = 4.

CLK_GPIO_DB_DIV_8 

GPIO Clock Debounce Divider = 8.

CLK_GPIO_DB_DIV_16 

GPIO Clock Debounce Divider = 16.

CLK_GPIO_DB_DIV_32 

GPIO Clock Debounce Divider = 32.

CLK_GPIO_DB_DIV_64 

GPIO Clock Debounce Divider = 64.

CLK_GPIO_DB_DIV_128 

GPIO Clock Debounce Divider = 128.

Definition at line 72 of file clk.h.

GPIO clock debounce divider type.

Enumerator
CLK_GPIO_DB_DIV_1 

GPIO Clock Debounce Divider = 1.

CLK_GPIO_DB_DIV_2 

GPIO Clock Debounce Divider = 2.

CLK_GPIO_DB_DIV_4 

GPIO Clock Debounce Divider = 4.

CLK_GPIO_DB_DIV_8 

GPIO Clock Debounce Divider = 8.

CLK_GPIO_DB_DIV_16 

GPIO Clock Debounce Divider = 16.

CLK_GPIO_DB_DIV_32 

GPIO Clock Debounce Divider = 32.

CLK_GPIO_DB_DIV_64 

GPIO Clock Debounce Divider = 64.

CLK_GPIO_DB_DIV_128 

GPIO Clock Debounce Divider = 128.

CLK_GPIO_DB_DIV_1 

GPIO Clock Debounce Divider = 1.

CLK_GPIO_DB_DIV_2 

GPIO Clock Debounce Divider = 2.

CLK_GPIO_DB_DIV_4 

GPIO Clock Debounce Divider = 4.

CLK_GPIO_DB_DIV_8 

GPIO Clock Debounce Divider = 8.

CLK_GPIO_DB_DIV_16 

GPIO Clock Debounce Divider = 16.

CLK_GPIO_DB_DIV_32 

GPIO Clock Debounce Divider = 32.

CLK_GPIO_DB_DIV_64 

GPIO Clock Debounce Divider = 64.

CLK_GPIO_DB_DIV_128 

GPIO Clock Debounce Divider = 128.

Definition at line 73 of file clk.h.

Peripheral clock divider type.

Enumerator
CLK_PERIPH_DIV_1 

Peripheral Clock Divider = 1.

CLK_PERIPH_DIV_2 

Peripheral Clock Divider = 2.

CLK_PERIPH_DIV_4 

Peripheral Clock Divider = 4.

CLK_PERIPH_DIV_8 

Peripheral Clock Divider = 8.

CLK_PERIPH_DIV_1 

Peripheral Clock Divider = 1.

CLK_PERIPH_DIV_2 

Peripheral Clock Divider = 2.

CLK_PERIPH_DIV_4 

Peripheral Clock Divider = 4.

CLK_PERIPH_DIV_8 

Peripheral Clock Divider = 8.

Definition at line 62 of file clk.h.

Peripheral clock divider type.

Enumerator
CLK_PERIPH_DIV_1 

Peripheral Clock Divider = 1.

CLK_PERIPH_DIV_2 

Peripheral Clock Divider = 2.

CLK_PERIPH_DIV_4 

Peripheral Clock Divider = 4.

CLK_PERIPH_DIV_8 

Peripheral Clock Divider = 8.

CLK_PERIPH_DIV_1 

Peripheral Clock Divider = 1.

CLK_PERIPH_DIV_2 

Peripheral Clock Divider = 2.

CLK_PERIPH_DIV_4 

Peripheral Clock Divider = 4.

CLK_PERIPH_DIV_8 

Peripheral Clock Divider = 8.

Definition at line 63 of file clk.h.

RTC clock divider type.

Enumerator
CLK_RTC_DIV_1 

Real Time Clock Divider = 1.

CLK_RTC_DIV_2 

Real Time Clock Divider = 2.

CLK_RTC_DIV_4 

Real Time Clock Divider = 4.

CLK_RTC_DIV_8 

Real Time Clock Divider = 8.

CLK_RTC_DIV_16 

Real Time Clock Divider = 16.

CLK_RTC_DIV_32 

Real Time Clock Divider = 32.

CLK_RTC_DIV_64 

Real Time Clock Divider = 64.

CLK_RTC_DIV_128 

Real Time Clock Divider = 128.

CLK_RTC_DIV_256 

Real Time Clock Divider = 256.

CLK_RTC_DIV_512 

Real Time Clock Divider = 512.

CLK_RTC_DIV_1024 

Real Time Clock Divider = 1024.

CLK_RTC_DIV_2048 

Real Time Clock Divider = 2048.

CLK_RTC_DIV_4096 

Real Time Clock Divider = 4096.

CLK_RTC_DIV_8192 

Real Time Clock Divider = 8192.

CLK_RTC_DIV_16384 

Real Time Clock Divider = 16384.

CLK_RTC_DIV_32768 

Real Time Clock Divider = 32768.

CLK_RTC_DIV_1 

Real Time Clock Divider = 1.

CLK_RTC_DIV_2 

Real Time Clock Divider = 2.

CLK_RTC_DIV_4 

Real Time Clock Divider = 4.

CLK_RTC_DIV_8 

Real Time Clock Divider = 8.

CLK_RTC_DIV_16 

Real Time Clock Divider = 16.

CLK_RTC_DIV_32 

Real Time Clock Divider = 32.

CLK_RTC_DIV_64 

Real Time Clock Divider = 64.

CLK_RTC_DIV_128 

Real Time Clock Divider = 128.

CLK_RTC_DIV_256 

Real Time Clock Divider = 256.

CLK_RTC_DIV_512 

Real Time Clock Divider = 512.

CLK_RTC_DIV_1024 

Real Time Clock Divider = 1024.

CLK_RTC_DIV_2048 

Real Time Clock Divider = 2048.

CLK_RTC_DIV_4096 

Real Time Clock Divider = 4096.

CLK_RTC_DIV_8192 

Real Time Clock Divider = 8192.

CLK_RTC_DIV_16384 

Real Time Clock Divider = 16384.

CLK_RTC_DIV_32768 

Real Time Clock Divider = 32768.

Definition at line 96 of file clk.h.

RTC clock divider type.

Enumerator
CLK_RTC_DIV_1 

Real Time Clock Divider = 1.

CLK_RTC_DIV_2 

Real Time Clock Divider = 2.

CLK_RTC_DIV_4 

Real Time Clock Divider = 4.

CLK_RTC_DIV_8 

Real Time Clock Divider = 8.

CLK_RTC_DIV_16 

Real Time Clock Divider = 16.

CLK_RTC_DIV_32 

Real Time Clock Divider = 32.

CLK_RTC_DIV_64 

Real Time Clock Divider = 64.

CLK_RTC_DIV_128 

Real Time Clock Divider = 128.

CLK_RTC_DIV_256 

Real Time Clock Divider = 256.

CLK_RTC_DIV_512 

Real Time Clock Divider = 512.

CLK_RTC_DIV_1024 

Real Time Clock Divider = 1024.

CLK_RTC_DIV_2048 

Real Time Clock Divider = 2048.

CLK_RTC_DIV_4096 

Real Time Clock Divider = 4096.

CLK_RTC_DIV_8192 

Real Time Clock Divider = 8192.

CLK_RTC_DIV_16384 

Real Time Clock Divider = 16384.

CLK_RTC_DIV_32768 

Real Time Clock Divider = 32768.

CLK_RTC_DIV_1 

Real Time Clock Divider = 1.

CLK_RTC_DIV_2 

Real Time Clock Divider = 2.

CLK_RTC_DIV_4 

Real Time Clock Divider = 4.

CLK_RTC_DIV_8 

Real Time Clock Divider = 8.

CLK_RTC_DIV_16 

Real Time Clock Divider = 16.

CLK_RTC_DIV_32 

Real Time Clock Divider = 32.

CLK_RTC_DIV_64 

Real Time Clock Divider = 64.

CLK_RTC_DIV_128 

Real Time Clock Divider = 128.

CLK_RTC_DIV_256 

Real Time Clock Divider = 256.

CLK_RTC_DIV_512 

Real Time Clock Divider = 512.

CLK_RTC_DIV_1024 

Real Time Clock Divider = 1024.

CLK_RTC_DIV_2048 

Real Time Clock Divider = 2048.

CLK_RTC_DIV_4096 

Real Time Clock Divider = 4096.

CLK_RTC_DIV_8192 

Real Time Clock Divider = 8192.

CLK_RTC_DIV_16384 

Real Time Clock Divider = 16384.

CLK_RTC_DIV_32768 

Real Time Clock Divider = 32768.

Definition at line 97 of file clk.h.

System clock divider type.

Enumerator
CLK_SYS_DIV_1 

Clock Divider = 1.

CLK_SYS_DIV_2 

Clock Divider = 2.

CLK_SYS_DIV_4 

Clock Divider = 4.

CLK_SYS_DIV_8 

Clock Divider = 8.

CLK_SYS_DIV_16 

Clock Divider = 16.

CLK_SYS_DIV_32 

Clock Divider = 32.

CLK_SYS_DIV_64 

Clock Divider = 64.

CLK_SYS_DIV_128 

Clock Divider = 128.

CLK_SYS_DIV_1 

Clock Divider = 1.

CLK_SYS_DIV_2 

Clock Divider = 2.

CLK_SYS_DIV_4 

Clock Divider = 4.

CLK_SYS_DIV_8 

Clock Divider = 8.

Definition at line 36 of file clk.h.

System clock divider type.

Enumerator
CLK_SYS_DIV_1 

Clock Divider = 1.

CLK_SYS_DIV_2 

Clock Divider = 2.

CLK_SYS_DIV_4 

Clock Divider = 4.

CLK_SYS_DIV_8 

Clock Divider = 8.

CLK_SYS_DIV_16 

Clock Divider = 16.

CLK_SYS_DIV_32 

Clock Divider = 32.

CLK_SYS_DIV_64 

Clock Divider = 64.

CLK_SYS_DIV_128 

Clock Divider = 128.

CLK_SYS_DIV_1 

Clock Divider = 1.

CLK_SYS_DIV_2 

Clock Divider = 2.

CLK_SYS_DIV_4 

Clock Divider = 4.

CLK_SYS_DIV_8 

Clock Divider = 8.

Definition at line 39 of file clk.h.

System clock mode type.

Enumerator
CLK_SYS_HYB_OSC_32MHZ 

32MHz Hybrid Oscillator Clock.

CLK_SYS_HYB_OSC_16MHZ 

16MHz Hybrid Oscillator Clock.

CLK_SYS_HYB_OSC_8MHZ 

8MHz Hybrid Oscillator Clock.

CLK_SYS_HYB_OSC_4MHZ 

4MHz Hybrid Oscillator Clock.

CLK_SYS_RTC_OSC 

Real Time Clock.

CLK_SYS_CRYSTAL_OSC 

Crystal Oscillator Clock.

CLK_SYS_HYB_OSC_32MHZ 

32MHz Hybrid Oscillator Clock.

CLK_SYS_HYB_OSC_16MHZ 

16MHz Hybrid Oscillator Clock.

CLK_SYS_HYB_OSC_8MHZ 

8MHz Hybrid Oscillator Clock.

CLK_SYS_HYB_OSC_4MHZ 

4MHz Hybrid Oscillator Clock.

CLK_SYS_RTC_OSC 

Real Time Clock.

CLK_SYS_CRYSTAL_OSC 

Crystal Oscillator Clock.

Definition at line 50 of file clk.h.

System clock mode type.

Enumerator
CLK_SYS_HYB_OSC_32MHZ 

32MHz Hybrid Oscillator Clock.

CLK_SYS_HYB_OSC_16MHZ 

16MHz Hybrid Oscillator Clock.

CLK_SYS_HYB_OSC_8MHZ 

8MHz Hybrid Oscillator Clock.

CLK_SYS_HYB_OSC_4MHZ 

4MHz Hybrid Oscillator Clock.

CLK_SYS_RTC_OSC 

Real Time Clock.

CLK_SYS_CRYSTAL_OSC 

Crystal Oscillator Clock.

CLK_SYS_HYB_OSC_32MHZ 

32MHz Hybrid Oscillator Clock.

CLK_SYS_HYB_OSC_16MHZ 

16MHz Hybrid Oscillator Clock.

CLK_SYS_HYB_OSC_8MHZ 

8MHz Hybrid Oscillator Clock.

CLK_SYS_HYB_OSC_4MHZ 

4MHz Hybrid Oscillator Clock.

CLK_SYS_RTC_OSC 

Real Time Clock.

CLK_SYS_CRYSTAL_OSC 

Crystal Oscillator Clock.

Definition at line 51 of file clk.h.

Function Documentation

int clk_adc_set_div ( const uint16_t  div)

Change divider value of ADC clock.

Change ADC clock divider value. The new divider value is set to N, where N is the value set by the function and is between 1 and 1024.

Parameters
[in]divDivider value for the ADC clock.
Returns
Standard errno return type for QMSI.
Return values
0on success.
Negativeerrno for possible error codes.

Definition at line 249 of file clk.c.

int clk_dma_disable ( void  )

Disable the DMA clock.

Disable the DMA clock by clearing the corresponding bit in the AHB Control register.

Returns
Standard errno return type for QMSI.
Return values
0on success.
Negativeerrno for possible error codes.

Definition at line 369 of file clk.c.

int clk_dma_enable ( void  )

Enable the DMA clock.

Enable the DMA clock by setting the corresponding bit in the AHB Control register. By default the DMA clock is disabled.

Returns
Standard errno return type for QMSI.
Return values
0on success.
Negativeerrno for possible error codes.

Definition at line 362 of file clk.c.

Referenced by qm_dma_init().

int clk_ext_set_div ( const clk_ext_div_t  div)

Change divider value of external clock.

Change External clock divider value. The maximum divisor is /8.

Parameters
[in]divDivider value for the external clock.
Returns
Standard errno return type for QMSI.
Return values
0on success.
Negativeerrno for possible error codes.

Definition at line 293 of file clk.c.

References CLK_EXT_DIV_8.

int clk_gpio_db_set_div ( const clk_gpio_db_div_t  div)

Change divider value of GPIO debounce clock.

Change GPIO debounce clock divider value. The maximum divisor is /128.

Parameters
[in]divDivider value for the GPIO debounce clock.
Returns
Standard errno return type for QMSI.
Return values
0on success.
Negativeerrno for possible error codes.

Definition at line 279 of file clk.c.

References CLK_GPIO_DB_DIV_128.

int clk_periph_disable ( const clk_periph_t  clocks)

Disable clocks for peripherals / registers.

Parameters
[in]clocksWhich peripheral and register clocks to disable.
Returns
Standard errno return type for QMSI.
Return values
0on success.
Negativeerrno for possible error codes.

Definition at line 333 of file clk.c.

References CLK_PERIPH_ALL, SOCW_EVENT_REGISTER, and SOCW_REG_CCU_PERIPH_CLK_GATE_CTL.

Referenced by qm_power_soc_deep_sleep(), and qm_power_soc_sleep().

int clk_periph_enable ( const clk_periph_t  clocks)

Enable clocks for peripherals / registers.

Parameters
[in]clocksWhich peripheral and register clocks to enable.
Returns
Standard errno return type for QMSI.
Return values
0on success.
Negativeerrno for possible error codes.

Definition at line 319 of file clk.c.

References CLK_PERIPH_ALL, SOCW_EVENT_REGISTER, and SOCW_REG_CCU_PERIPH_CLK_GATE_CTL.

Referenced by qm_power_soc_deep_sleep_restore(), and qm_wdt_start().

int clk_periph_set_div ( const clk_periph_div_t  div)

Change divider value of peripheral clock.

Change Peripheral clock divider value. The maximum divisor is /8. Refer to the list of supported peripherals for your SoC.

Parameters
[in]divDivider value for the peripheral clock.
Returns
Standard errno return type for QMSI.
Return values
0on success.
Negativeerrno for possible error codes.

Definition at line 265 of file clk.c.

References CLK_PERIPH_DIV_8.

int clk_rtc_set_div ( const clk_rtc_div_t  div)

Change divider value of RTC.

Change RTC divider value. The maximum divisor is /32768.

Parameters
[in]divDivider value for the RTC.
Returns
Standard errno return type for QMSI.
Return values
0on success.
Negativeerrno for possible error codes.

Definition at line 306 of file clk.c.

References CLK_RTC_DIV_32768.

Referenced by qm_rtc_set_config().

uint32_t clk_sys_get_ticks_per_us ( void  )

Get number of system ticks per micro second.

Returns
uint32_t Number of system ticks per micro second.

Definition at line 347 of file clk.c.

Referenced by get_i2c_clk_freq_in_mhz(), and ss_clk_adc_set_div().

int clk_sys_set_mode ( const clk_sys_mode_t  mode,
const clk_sys_div_t  div 
)

Set clock mode and divisor.

Change the operating mode and clock divisor of the system clock source. Changing this clock speed affects all peripherals. This applies the correct trim code if available.

If trim code is not available, it is not computed and previous trim code is not modified.

Parameters
[in]modeSystem clock source operating mode.
[in]divSystem clock divisor.
Returns
Standard errno return type for QMSI.
Return values
0on success.
Negativeerrno for possible error codes.

Definition at line 100 of file clk.c.

References CLK_SYS_CRYSTAL_OSC, CLK_SYS_HYB_OSC_16MHZ, CLK_SYS_HYB_OSC_32MHZ, CLK_SYS_HYB_OSC_4MHZ, CLK_SYS_HYB_OSC_8MHZ, CLK_SYS_RTC_OSC, clk_trim_apply(), and SOCW_EVENT_FREQ.

Referenced by clk_sys_usb_enable(), qm_power_soc_deep_sleep(), and qm_power_soc_sleep().

void clk_sys_udelay ( uint32_t  microseconds)

Idle loop the processor for at least the value given in microseconds.

This function will wait until at least the given number of microseconds has elapsed since calling this function.

Note: It is dependent on the system clock speed. The delay parameter does not include, calling the function, returning from it, calculation setup and while loops.

Parameters
[in]microsecondsMinimum number of micro seconds to delay for.

Definition at line 352 of file clk.c.

Referenced by clk_sys_usb_disable(), clk_sys_usb_enable(), clk_trim_apply(), and qm_usb_ep_flush().

int clk_sys_usb_disable ( void  )

Disable the USB Clock mode.

This function will disable the USB Clock and PLL. The system clock will remain as CLK_SYS_CRYSTAL_OSC mode and CLK_SYS_DIV_1 divider.

Note: If the application must restore the original system clock mode / divisor it must explictly call clk_sys_set_mode() restoring the previous config. This can only be done after the USB clock mode is disabled.

Returns
Standard errno return type for QMSI.
Return values
0on success.
Negativeerrno for possible error codes.

Definition at line 386 of file clk.c.

References clk_sys_udelay().

Referenced by qm_usb_detach().

int clk_sys_usb_enable ( void  )

Enable the USB Clock mode.

For Quark SE, this function will set the system clock to CLK_SYS_CRYSTAL_OSC mode with CLK_SYS_DIV_1 divisor. It then will enable the USB Clock and PLL, blocking execution until the USB PLL lock is ready.

Note: Application must retain the original system clock mode / divisor in case it will need to restore it after disabling the usb clock.

Returns
Standard errno return type for QMSI.
Return values
0on success.
Negativeerrno for possible error codes.

Definition at line 356 of file clk.c.

References CLK_SYS_CRYSTAL_OSC, CLK_SYS_DIV_1, clk_sys_set_mode(), and clk_sys_udelay().

Referenced by qm_usb_attach().

int clk_trim_apply ( const uint32_t  value)

Apply silicon oscillator trim code.

Parameters
[in]valueTrim code to apply.
Returns
Standard errno return type for QMSI.
Return values
0on success.
Negativeerrno for possible error codes.

Definition at line 224 of file clk.c.

References clk_sys_udelay().

Referenced by clk_sys_set_mode().

int clk_trim_read ( uint32_t *const  value)

Read the silicon oscillator trim code for the current frequency.

Parameters
[out]valuePointer to store the trim code.
Returns
Standard errno return type for QMSI.
Return values
0on success.
Negativeerrno for possible error codes.

Definition at line 214 of file clk.c.

uint32_t get_i2c_clk_freq_in_mhz ( void  )

Get I2C clock frequency in MHz.

Returns
[uint32_t] I2C freq_in_mhz.

Definition at line 381 of file clk.c.

References clk_sys_get_ticks_per_us().