6 #include "qm_mailbox.h"
7 #include "qm_interrupt.h"
8 #include "qm_interrupt_router.h"
19 #if HAS_MAILBOX_LAKEMONT_DEST
21 #define ACTIVE_CORE_DEST QM_MBOX_TO_LMT
22 #define MBOX_ACTIVE_CORE_ALL_INT_MASK QM_IR_MBOX_LMT_ALL_INT_MASK
23 #define MBOX_INT_LOCK_MASK(N) QM_IR_MBOX_LMT_INT_LOCK_MASK(N)
24 #define MBOX_INT_LOCK_HALT_MASK(N) QM_IR_MBOX_LMT_INT_LOCK_HALT_MASK(N)
25 #define MBOX_IS_INT_MASK_EN(N) QM_IR_MBOX_IS_LMT_INT_MASK_EN(N)
26 #define MBOX_ENABLE_INT_MASK(N) QM_IR_MBOX_ENABLE_LMT_INT_MASK(N)
27 #define MBOX_DISABLE_INT_MASK(N) QM_IR_MBOX_DISABLE_LMT_INT_MASK(N)
31 #if HAS_MAILBOX_SENSOR_SUB_SYSTEM_DEST
33 #define ACTIVE_CORE_DEST QM_MBOX_TO_SS
34 #define MBOX_ACTIVE_CORE_ALL_INT_MASK QM_IR_MBOX_SS_ALL_INT_MASK
35 #define MBOX_INT_LOCK_MASK(N) QM_IR_MBOX_SS_INT_LOCK_HALT_MASK(N)
36 #define MBOX_INT_LOCK_HALT_MASK(N) QM_IR_MBOX_SS_INT_LOCK_MASK(N)
37 #define MBOX_IS_INT_MASK_EN(N) QM_IR_MBOX_IS_SS_INT_MASK_EN(N)
38 #define MBOX_ENABLE_INT_MASK(N) QM_IR_MBOX_ENABLE_SS_INT_MASK(N)
39 #define MBOX_DISABLE_INT_MASK(N) QM_IR_MBOX_DISABLE_SS_INT_MASK(N)
43 #define MBOX_CHECK_DESTINATION(_dest) (ACTIVE_CORE_DEST == (_dest))
44 #define MBOX_CHECK_POLLING_MODE(_mode) (QM_MBOX_POLLING_MODE == (_mode))
46 static void mailbox_isr_handler(
void);
64 static qm_mailbox_info_t mailbox_devs[NUM_MAILBOXES];
68 mailbox_isr_handler();
69 QM_ISR_EOI(QM_IRQ_MAILBOX_0_INT_VECTOR);
72 static void mailbox_isr_handler(
void)
77 uint16_t chall_sts = QM_MAILBOX->mbox_chall_sts;
79 mask = MBOX_ACTIVE_CORE_ALL_INT_MASK;
80 for (i = 0; chall_sts; i++, chall_sts >>= 2) {
81 if ((chall_sts & QM_MBOX_CH_STS_CTRL_INT) == 0) {
87 if (mbox_reg[i].ch_sts & QM_MBOX_CH_STS_CTRL_INT) {
88 if (NULL != mailbox_devs[i].callback) {
90 mailbox_devs[i].callback(
91 mailbox_devs[i].callback_data);
94 mbox_reg[i].
ch_sts = QM_MBOX_CH_STS_CTRL_INT;
103 QM_CHECK((
QM_MBOX_CH_0 <= mbox_ch) && (mbox_ch < NUM_MAILBOXES),
105 qm_mailbox_info_t *device = &mailbox_devs[mbox_ch];
108 QM_IR_MASK_INT(QM_IRQ_MAILBOX_0_INT);
111 device->dest = config->
dest;
114 if (QM_MBOX_UNUSED != config->
dest) {
117 QM_CHECK(NULL != config->
callback, -EINVAL);
120 device->callback = config->
callback;
122 device->callback_data = config->callback_data;
129 if (!(MBOX_INT_LOCK_MASK(mbox_ch))) {
132 MBOX_ENABLE_INT_MASK(mbox_ch);
136 QM_CHECK(MBOX_IS_INT_MASK_EN(mbox_ch), -EIO);
142 if (!(MBOX_INT_LOCK_MASK(mbox_ch))) {
145 MBOX_DISABLE_INT_MASK(mbox_ch);
148 device->callback = NULL;
149 device->callback_data = 0;
153 if (!(MBOX_INT_LOCK_MASK(mbox_ch))) {
156 MBOX_DISABLE_INT_MASK(mbox_ch);
160 device->dest = QM_MBOX_UNUSED;
162 device->callback = NULL;
163 device->callback_data = 0;
167 QM_IR_UNMASK_INT(QM_IRQ_MAILBOX_0_INT);
173 QM_CHECK((
QM_MBOX_CH_0 <= mbox_ch) && (mbox_ch < NUM_MAILBOXES),
175 QM_CHECK(NULL != msg, -EINVAL);
180 status = QM_MAILBOX->mbox[mbox_ch].
ch_sts;
183 if (
false == (status & (QM_MBOX_CH_STS_CTRL_INT | QM_MBOX_CH_STS))) {
190 mbox_reg->
ch_ctrl = msg->
ctrl | QM_MBOX_CH_CTRL_INT;
200 QM_CHECK((
QM_MBOX_CH_0 <= mbox_ch) && (mbox_ch < NUM_MAILBOXES),
202 QM_CHECK(NULL != msg, -EINVAL);
209 if (MBOX_CHECK_DESTINATION(mailbox_devs[mbox_ch].dest)) {
210 status = mbox_reg->
ch_sts;
213 if (status & QM_MBOX_CH_STS) {
216 msg->
ctrl = mbox_reg->
ch_ctrl & (~QM_MBOX_CH_CTRL_INT);
222 if (MBOX_CHECK_POLLING_MODE(
223 mailbox_devs[mbox_ch].mode)) {
228 mbox_reg->
ch_sts = QM_MBOX_CH_STS_CTRL_INT;
234 mbox_reg->
ch_sts = QM_MBOX_CH_STS;
251 QM_CHECK((
QM_MBOX_CH_0 <= mbox_ch) && (mbox_ch < NUM_MAILBOXES),
253 QM_CHECK(NULL != status, -EINVAL);
255 *status = QM_MAILBOX->mbox[mbox_ch].ch_sts;
void(* qm_mbox_callback_t)(void *data)
Definition of the mailbox callback function prototype.
int qm_mbox_ch_read(const qm_mbox_ch_t mbox_ch, qm_mbox_msg_t *const msg)
Read specified mailbox channel.
qm_mbox_ch_t
Mailbox channel identifiers.
QM_RW uint32_t ch_data[4]
Channel Payload Data Word 0.
qm_mbox_destination_t dest
< Mailbox Destination
QM_RW uint32_t ch_ctrl
Channel Control Word.
Mailbox channel operates in polling mode.
uint32_t data[QM_MBOX_PAYLOAD_NUM]
Mailbox data buffer.
int qm_mbox_ch_write(const qm_mbox_ch_t mbox_ch, const qm_mbox_msg_t *const msg)
Write to a specified mailbox channel.
int qm_mbox_ch_get_status(const qm_mbox_ch_t mbox_ch, qm_mbox_ch_status_t *const status)
Retrieve the specified mailbox channel status.
uint32_t ctrl
Control word - bits 30 to 0 used as data/message id, bit 31 triggers channel interrupt when set by th...
Definition of the mailbox message.
QM_ISR_DECLARE(qm_mailbox_0_isr)
ISR for Mailbox interrupt.
QM_RW uint32_t ch_sts
Channel status.
int qm_mbox_ch_set_config(const qm_mbox_ch_t mbox_ch, const qm_mbox_config_t *const config)
Set the mailbox channel configuration.
Mailbox register structure.
qm_mbox_destination_t
Definition of the mailbox direction of operation The direction of communication for each channel is c...
Mailbox channel operates in interrupt mode.
qm_mbox_mode_t mode
Message callback.
qm_mbox_mode_t
Definition of the mailbox mode of operation, interrupt mode or polling mode.
Mailbox Configuration Structure.
qm_mbox_callback_t callback
Callback function data to return via the callback function.
qm_mbox_ch_status_t
Mailbox channel status return codes.