5 #ifndef __REGISTERS_H__
6 #define __REGISTERS_H__
9 #include "qm_interrupt_router_regs.h"
10 #include "qm_soc_interrupts.h"
11 #include "flash_layout.h"
20 #define QUARK_D2000 (1)
22 #define HAS_SOC_CONTEXT_RETENTION (1)
36 QM_RW uint32_t reserved;
45 QM_RW uint32_t reserved1;
57 #define QM_SCSS_CCU ((qm_scss_ccu_reg_t *)(&test_scss_ccu))
60 #define QM_SCSS_CCU_BASE (0xB0800000)
61 #define QM_SCSS_CCU ((qm_scss_ccu_reg_t *)QM_SCSS_CCU_BASE)
65 #define QM_GPS0_BIT_FM (0)
68 #define QM_OSC0_MODE_SEL BIT(3)
69 #define QM_OSC0_PD BIT(2)
70 #define QM_OSC1_PD BIT(1)
73 #define QM_OSC0_EN_CRYSTAL BIT(0)
76 #define OSC0_CFG1_OSC0_FADJ_XTAL_MASK (0x000F0000)
77 #define OSC0_CFG1_OSC0_FADJ_XTAL_OFFS (16)
78 #define OSC0_CFG0_OSC0_XTAL_COUNT_VALUE_MASK (0x00600000)
79 #define OSC0_CFG0_OSC0_XTAL_COUNT_VALUE_OFFS (21)
82 #define OSC0_CFG1_FTRIMOTP_MASK (0x3FF00000)
83 #define OSC0_CFG1_FTRIMOTP_OFFS (20)
84 #define OSC0_CFG1_SI_FREQ_SEL_MASK (0x00000300)
85 #define OSC0_CFG1_SI_FREQ_SEL_OFFS (8)
87 #define QM_OSC0_LOCK_SI BIT(0)
88 #define QM_OSC0_LOCK_XTAL BIT(1)
89 #define QM_OSC0_EN_SI_OSC BIT(1)
91 #define QM_SI_OSC_1V2_MODE BIT(0)
94 #define QM_CCU_PERIPH_PCLK_DIV_OFFSET (1)
95 #define QM_CCU_PERIPH_PCLK_DIV_EN BIT(0)
98 #define QM_CCU_SYS_CLK_SEL BIT(0)
99 #define QM_CCU_PERIPH_CLK_EN BIT(1)
100 #define QM_CCU_ADC_CLK_DIV_OFFSET (16)
101 #define QM_CCU_ADC_CLK_DIV_DEF_MASK (0xFC00FFFF)
102 #define QM_CCU_PERIPH_PCLK_DIV_DEF_MASK (0xFFFFFFF8)
103 #define QM_CCU_RTC_CLK_EN BIT(1)
104 #define QM_CCU_RTC_CLK_DIV_EN BIT(2)
105 #define QM_CCU_SYS_CLK_DIV_EN BIT(7)
106 #define QM_CCU_SYS_CLK_DIV_MASK (0x00000700)
108 #define QM_OSC0_SI_FREQ_SEL_DEF_MASK (0xFFFFFCFF)
109 #define QM_CCU_SYS_CLK_DIV_DEF_MASK (0xFFFFF47F)
110 #define QM_OSC0_SI_FREQ_SEL_4MHZ (3 >> 8)
112 #define QM_CCU_EXTERN_DIV_OFFSET (3)
113 #define QM_CCU_EXT_CLK_DIV_EN BIT(2)
114 #define QM_CCU_GPIO_DB_DIV_OFFSET (2)
115 #define QM_CCU_GPIO_DB_CLK_DIV_EN BIT(1)
116 #define QM_CCU_GPIO_DB_CLK_EN BIT(0)
117 #define QM_CCU_RTC_CLK_DIV_OFFSET (3)
118 #define QM_CCU_SYS_CLK_DIV_OFFSET (8)
119 #define QM_CCU_GPIO_DB_CLK_DIV_DEF_MASK (0xFFFFFFE1)
120 #define QM_CCU_EXT_CLK_DIV_DEF_MASK (0xFFFFFFE3)
121 #define QM_CCU_RTC_CLK_DIV_DEF_MASK (0xFFFFFF83)
122 #define QM_CCU_DMA_CLK_EN BIT(6)
123 #define QM_CCU_WAKE_MASK_RTC_BIT BIT(2)
124 #define QM_CCU_WAKE_MASK_GPIO_BIT BIT(15)
125 #define QM_CCU_WAKE_MASK_COMPARATOR_BIT BIT(14)
126 #define QM_CCU_WAKE_MASK_GPIO_BIT BIT(15)
128 #define QM_HYB_OSC_PD_LATCH_EN BIT(14)
129 #define QM_RTC_OSC_PD_LATCH_EN BIT(15)
130 #define QM_CCU_EXIT_TO_HYBOSC BIT(4)
131 #define QM_CCU_MEM_HALT_EN BIT(3)
132 #define QM_CCU_CPU_HALT_EN BIT(2)
134 #define QM_WAKE_PROBE_MODE_MASK BIT(13)
149 QM_RW uint32_t reserved;
154 QM_RW uint32_t reserved1[3];
162 #define QM_SCSS_GP ((qm_scss_gp_reg_t *)(&test_scss_gp))
165 #define QM_SCSS_GP_BASE (0xB0800100)
166 #define QM_SCSS_GP ((qm_scss_gp_reg_t *)QM_SCSS_GP_BASE)
169 #define QM_GPS0_POWER_STATES_MASK (BIT(6) | BIT(7) | BIT(8) | BIT(9))
170 #define QM_GPS0_POWER_STATE_SLEEP BIT(6)
171 #define QM_GPS0_POWER_STATE_DEEP_SLEEP BIT(7)
187 QM_RW uint32_t reserved[6];
193 #define QM_SCSS_CMP ((qm_scss_cmp_reg_t *)(&test_scss_cmp))
196 #define QM_SCSS_CMP_BASE (0xB0800300)
197 #define QM_SCSS_CMP ((qm_scss_cmp_reg_t *)QM_SCSS_CMP_BASE)
200 #define QM_AC_HP_COMPARATORS_MASK (0x7FFC0)
212 QM_RW uint32_t reserved[5];
214 QM_RW uint32_t reserved1;
216 QM_RW uint32_t reserved2[3];
219 QM_RW uint32_t reserved3[7];
225 #define QM_SCSS_PMU ((qm_scss_pmu_reg_t *)(&test_scss_pmu))
228 #define QM_SCSS_PMU_BASE (0xB0800540)
229 #define QM_SCSS_PMU ((qm_scss_pmu_reg_t *)QM_SCSS_PMU_BASE)
232 #define QM_P_STS_HALT_INTERRUPT_REDIRECTION BIT(26)
238 #define QM_AON_VR_ROK_BUF_VREG_STATUS BIT(15)
239 #define QM_AON_VR_ROK_BUF_VREG_MASK BIT(9)
240 #define QM_AON_VR_VREG_SEL BIT(8)
241 #define QM_AON_VR_PASS_CODE (0x9DC4 << 16)
242 #define QM_AON_VR_VSEL_MASK (0xFFE0)
243 #define QM_AON_VR_VSEL_1V35 (0xB)
244 #define QM_AON_VR_VSEL_1V8 (0x10)
245 #define QM_AON_VR_VSTRB BIT(5)
269 #define qm_aonc_context_t uint8_t
271 #define HAS_AONPT_BUSY_BIT (0)
273 #define QM_AONC_ENABLE (BIT(0))
274 #define QM_AONC_DISABLE (~QM_AONC_ENABLE)
276 #define QM_AONPT_INTERRUPT (BIT(0))
278 #define QM_AONPT_CLR (BIT(0))
279 #define QM_AONPT_RST (BIT(1))
285 #define QM_AONC test_aonc
289 #define QM_AONC_0_BASE (0xB0800700)
290 #define QM_AONC qm_aonc
303 QM_RW uint32_t reserved[2];
309 #define QM_SCSS_PERIPHERAL ((qm_scss_peripheral_reg_t *)(&test_scss_peripheral))
312 #define QM_SCSS_PERIPHERAL_BASE (0xB0800804)
313 #define QM_SCSS_PERIPHERAL ((qm_scss_peripheral_reg_t *)QM_SCSS_PERIPHERAL_BASE)
325 QM_RW uint32_t pmux_pullup[1];
326 QM_RW uint32_t reserved[3];
327 QM_RW uint32_t pmux_slew[1];
328 QM_RW uint32_t reserved1[3];
329 QM_RW uint32_t pmux_in_en[1];
330 QM_RW uint32_t reserved2[3];
331 QM_RW uint32_t pmux_sel[2];
332 QM_RW uint32_t reserved3[5];
336 QM_RW uint32_t reserved4[2];
342 #define QM_SCSS_PMUX ((qm_scss_pmux_reg_t *)(&test_scss_pmux))
345 #define QM_SCSS_PMUX_BASE (0xB0800900)
346 #define QM_SCSS_PMUX ((qm_scss_pmux_reg_t *)QM_SCSS_PMUX_BASE)
368 #define QM_SCSS_INFO ((qm_scss_info_reg_t *)(&test_scss_info))
371 #define QM_SCSS_INFO_BASE (0xB0801000)
372 #define QM_SCSS_INFO ((qm_scss_info_reg_t *)QM_SCSS_INFO_BASE)
383 typedef enum { QM_PWM_0 = 0, QM_PWM_NUM }
qm_pwm_t;
386 typedef enum { QM_PWM_ID_0 = 0, QM_PWM_ID_1, QM_PWM_ID_NUM }
qm_pwm_id_t;
400 QM_RW uint32_t reserved[30];
406 timer_loadcount2[QM_PWM_ID_NUM];
409 #define qm_pwm_context_t uint8_t
414 #define QM_PWM test_pwm
419 #define QM_PWM_BASE (0xB0000800)
421 #define QM_PWM qm_pwm
424 #define PWM_START (1)
426 #define QM_PWM_CONF_MODE_MASK (0xA)
427 #define QM_PWM_CONF_INT_EN_MASK (0x4)
429 #define QM_PWM_INTERRUPT_MASK_OFFSET (0x2)
431 #define NUM_PWM_CONTROLLER_INTERRUPTS (1)
449 #define QM_PWM_TIMERNCONTROLREG_TIMER_ENABLE (BIT(0))
450 #define QM_PWM_TIMERNCONTROLREG_TIMER_MODE (BIT(1))
451 #define QM_PWM_TIMERNCONTROLREG_TIMER_INTERRUPT_MASK (BIT(2))
452 #define QM_PWM_TIMERNCONTROLREG_TIMER_PWM (BIT(3))
454 #define QM_PWM_MODE_TIMER_FREE_RUNNING_VALUE (0)
455 #define QM_PWM_MODE_TIMER_COUNT_VALUE (QM_PWM_TIMERNCONTROLREG_TIMER_MODE)
456 #define QM_PWM_MODE_PWM_VALUE \
457 (QM_PWM_TIMERNCONTROLREG_TIMER_PWM | QM_PWM_TIMERNCONTROLREG_TIMER_MODE)
467 typedef enum { QM_WDT_0 = 0, QM_WDT_NUM }
qm_wdt_t;
487 #define qm_wdt_context_t uint8_t
492 #define QM_WDT test_wdt
497 #define QM_WDT_0_BASE (0xB0000000)
500 #define QM_WDT qm_wdt
504 #define QM_WDT_CR_WDT_ENABLE (BIT(0))
506 #define QM_WDT_CR_RMOD (BIT(1))
508 #define QM_WDT_CR_RMOD_OFFSET (1)
510 #define QM_WDT_TORR_TOP_MASK (0xF)
512 #define QM_WDT_RELOAD_VALUE (0x76)
514 #define NUM_WDT_CONTROLLERS (1)
516 #define HAS_WDT_PAUSE (0)
518 #define HAS_SW_SOCWATCH (1)
520 #define QM_WDT_CLOCK_EN_MASK (BIT(10))
522 #define HAS_WDT_CLOCK_ENABLE (1)
557 #define QM_UART_LCR_BREAK BIT(6)
559 #define QM_UART_LCR_DLAB BIT(7)
562 #define QM_UART_MCR_RTS BIT(1)
564 #define QM_UART_MCR_LOOPBACK BIT(4)
566 #define QM_UART_MCR_AFCE BIT(5)
569 #define QM_UART_FCR_FIFOE BIT(0)
571 #define QM_UART_FCR_RFIFOR BIT(1)
573 #define QM_UART_FCR_XFIFOR BIT(2)
576 #define QM_UART_FCR_DEFAULT_TX_RX_THRESHOLD (0xB0)
578 #define QM_UART_FCR_TX_0_RX_1_2_THRESHOLD (0x80)
581 #define QM_UART_IIR_THR_EMPTY (0x02)
583 #define QM_UART_IIR_RECV_DATA_AVAIL (0x04)
585 #define QM_UART_IIR_RECV_LINE_STATUS (0x06)
587 #define QM_UART_IIR_CHAR_TIMEOUT (0x0C)
589 #define QM_UART_IIR_IID_MASK (0x0F)
592 #define QM_UART_LSR_DR BIT(0)
594 #define QM_UART_LSR_OE BIT(1)
596 #define QM_UART_LSR_PE BIT(2)
598 #define QM_UART_LSR_FE BIT(3)
600 #define QM_UART_LSR_BI BIT(4)
602 #define QM_UART_LSR_THRE BIT(5)
604 #define QM_UART_LSR_TEMT BIT(6)
606 #define QM_UART_LSR_RFE BIT(7)
609 #define QM_UART_IER_ERBFI BIT(0)
611 #define QM_UART_IER_ETBEI BIT(1)
613 #define QM_UART_IER_ELSI BIT(2)
615 #define QM_UART_IER_PTIME BIT(7)
618 #define QM_UART_LSR_ERROR_BITS \
619 (QM_UART_LSR_OE | QM_UART_LSR_PE | QM_UART_LSR_FE | QM_UART_LSR_BI)
622 #define QM_UART_FIFO_DEPTH (16)
624 #define QM_UART_FIFO_HALF_DEPTH (QM_UART_FIFO_DEPTH / 2)
627 #define QM_UART_CFG_BAUD_DLH_OFFS 16
629 #define QM_UART_CFG_BAUD_DLL_OFFS 8
631 #define QM_UART_CFG_BAUD_DLF_OFFS 0
633 #define QM_UART_CFG_BAUD_DLH_MASK (0xFF << QM_UART_CFG_BAUD_DLH_OFFS)
635 #define QM_UART_CFG_BAUD_DLL_MASK (0xFF << QM_UART_CFG_BAUD_DLL_OFFS)
637 #define QM_UART_CFG_BAUD_DLF_MASK (0xFF << QM_UART_CFG_BAUD_DLF_OFFS)
640 #define QM_UART_CFG_BAUD_DL_PACK(dlh, dll, dlf) \
641 (dlh << QM_UART_CFG_BAUD_DLH_OFFS | dll << QM_UART_CFG_BAUD_DLL_OFFS | \
642 dlf << QM_UART_CFG_BAUD_DLF_OFFS)
645 #define QM_UART_CFG_BAUD_DLH_UNPACK(packed) \
646 ((packed & QM_UART_CFG_BAUD_DLH_MASK) >> QM_UART_CFG_BAUD_DLH_OFFS)
648 #define QM_UART_CFG_BAUD_DLL_UNPACK(packed) \
649 ((packed & QM_UART_CFG_BAUD_DLL_MASK) >> QM_UART_CFG_BAUD_DLL_OFFS)
651 #define QM_UART_CFG_BAUD_DLF_UNPACK(packed) \
652 ((packed & QM_UART_CFG_BAUD_DLF_MASK) >> QM_UART_CFG_BAUD_DLF_OFFS)
655 typedef enum { QM_UART_0 = 0, QM_UART_1, QM_UART_NUM }
qm_uart_t;
668 QM_RW uint32_t reserved[23];
670 QM_RW uint32_t reserved1[9];
682 QM_RW uint32_t padding[204];
685 #define qm_uart_context_t uint8_t
690 #define QM_UART test_uart
694 #define QM_UART_0_BASE (0xB0002000)
695 #define QM_UART_1_BASE (0xB0002400)
698 #define QM_UART qm_uart
709 typedef enum { QM_SPI_MST_0 = 0, QM_SPI_SLV_0, QM_SPI_NUM }
qm_spi_t;
740 QM_RW uint32_t dr[36];
742 QM_RW uint32_t padding[0x1C4];
745 #define qm_spi_context_t uint8_t
751 #define QM_SPI test_spi_controllers
755 #define QM_SPI_MST_0_BASE (0xB0001000)
757 #define QM_SPI qm_spi_controllers
760 #define QM_SPI_SLV_BASE (0xB0001800)
764 #define QM_SPI_CTRLR0_DFS_32_MASK (0x001F0000)
765 #define QM_SPI_CTRLR0_TMOD_MASK (0x00000300)
766 #define QM_SPI_CTRLR0_SCPOL_SCPH_MASK (0x000000C0)
767 #define QM_SPI_CTRLR0_FRF_MASK (0x00000030)
768 #define QM_SPI_CTRLR0_DFS_32_OFFSET (16)
769 #define QM_SPI_CTRLR0_TMOD_OFFSET (8)
770 #define QM_SPI_CTRLR0_SCPOL_SCPH_OFFSET (6)
771 #define QM_SPI_CTRLR0_FRF_OFFSET (4)
772 #define QM_SPI_CTRLR0_SLV_OE BIT(10)
775 #define QM_SPI_SSIENR_SSIENR BIT(0)
778 #define QM_SPI_SR_BUSY BIT(0)
779 #define QM_SPI_SR_TFNF BIT(1)
780 #define QM_SPI_SR_TFE BIT(2)
781 #define QM_SPI_SR_RFNE BIT(3)
782 #define QM_SPI_SR_RFF BIT(4)
785 #define QM_SPI_IMR_MASK_ALL (0x00)
786 #define QM_SPI_IMR_TXEIM BIT(0)
787 #define QM_SPI_IMR_TXOIM BIT(1)
788 #define QM_SPI_IMR_RXUIM BIT(2)
789 #define QM_SPI_IMR_RXOIM BIT(3)
790 #define QM_SPI_IMR_RXFIM BIT(4)
793 #define QM_SPI_ISR_TXEIS BIT(0)
794 #define QM_SPI_ISR_TXOIS BIT(1)
795 #define QM_SPI_ISR_RXUIS BIT(2)
796 #define QM_SPI_ISR_RXOIS BIT(3)
797 #define QM_SPI_ISR_RXFIS BIT(4)
800 #define QM_SPI_RISR_TXEIR BIT(0)
801 #define QM_SPI_RISR_TXOIR BIT(1)
802 #define QM_SPI_RISR_RXUIR BIT(2)
803 #define QM_SPI_RISR_RXOIR BIT(3)
804 #define QM_SPI_RISR_RXFIR BIT(4)
807 #define QM_SPI_DMACR_RDMAE BIT(0)
808 #define QM_SPI_DMACR_TDMAE BIT(1)
818 typedef enum { QM_RTC_0 = 0, QM_RTC_NUM }
qm_rtc_t;
832 #define qm_rtc_context_t uint8_t
834 #define QM_RTC_CCR_INTERRUPT_ENABLE BIT(0)
835 #define QM_RTC_CCR_INTERRUPT_MASK BIT(1)
836 #define QM_RTC_CCR_ENABLE BIT(2)
842 #define QM_RTC test_rtc
847 #define QM_RTC_BASE (0xB0000400)
850 #define QM_RTC qm_rtc
861 typedef enum { QM_I2C_0 = 0, QM_I2C_NUM }
qm_i2c_t;
904 QM_RW uint32_t reserved;
915 QM_RW uint32_t reserved1[18];
921 #define qm_i2c_context_t uint8_t
927 #define QM_I2C test_i2c
931 #define QM_I2C_0_BASE (0xB0002800)
935 #define QM_I2C qm_i2c
938 #define QM_I2C_IC_ENABLE_CONTROLLER_EN BIT(0)
939 #define QM_I2C_IC_ENABLE_CONTROLLER_ABORT BIT(1)
940 #define QM_I2C_IC_ENABLE_STATUS_IC_EN BIT(0)
941 #define QM_I2C_IC_CON_MASTER_MODE BIT(0)
942 #define QM_I2C_IC_CON_SLAVE_DISABLE BIT(6)
943 #define QM_I2C_IC_CON_10BITADDR_MASTER BIT(4)
944 #define QM_I2C_IC_CON_10BITADDR_MASTER_OFFSET (4)
945 #define QM_I2C_IC_CON_10BITADDR_SLAVE BIT(3)
946 #define QM_I2C_IC_CON_10BITADDR_SLAVE_OFFSET (3)
947 #define QM_I2C_IC_CON_SPEED_OFFSET (1)
948 #define QM_I2C_IC_CON_SPEED_SS BIT(1)
949 #define QM_I2C_IC_CON_SPEED_FS_FSP BIT(2)
950 #define QM_I2C_IC_CON_SPEED_MASK (0x06)
951 #define QM_I2C_IC_CON_RESTART_EN BIT(5)
952 #define QM_I2C_IC_CON_STOP_DET_IFADDRESSED BIT(7)
953 #define QM_I2C_IC_DATA_CMD_READ BIT(8)
954 #define QM_I2C_IC_DATA_CMD_STOP_BIT_CTRL BIT(9)
955 #define QM_I2C_IC_DATA_CMD_LSB_MASK (0x000000FF)
956 #define QM_I2C_IC_RAW_INTR_STAT_RX_FULL BIT(2)
957 #define QM_I2C_IC_RAW_INTR_STAT_TX_ABRT BIT(6)
958 #define QM_I2C_IC_RAW_INTR_STAT_GEN_CALL BIT(11)
959 #define QM_I2C_IC_RAW_INTR_STAT_RESTART_DETECTED BIT(12)
960 #define QM_I2C_IC_TX_ABRT_SOURCE_NAK_MASK (0x1F)
961 #define QM_I2C_IC_TX_ABRT_SOURCE_ARB_LOST BIT(12)
962 #define QM_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT BIT(9)
963 #define QM_I2C_IC_TX_ABRT_SOURCE_ALL_MASK (0x1FFFF)
964 #define QM_I2C_IC_STATUS_BUSY_MASK (0x00000060)
965 #define QM_I2C_IC_STATUS_RFF BIT(4)
966 #define QM_I2C_IC_STATUS_RFNE BIT(3)
967 #define QM_I2C_IC_STATUS_TFE BIT(2)
968 #define QM_I2C_IC_STATUS_TNF BIT(1)
969 #define QM_I2C_IC_INTR_MASK_ALL (0x00)
970 #define QM_I2C_IC_INTR_MASK_RX_UNDER BIT(0)
971 #define QM_I2C_IC_INTR_MASK_RX_OVER BIT(1)
972 #define QM_I2C_IC_INTR_MASK_RX_FULL BIT(2)
973 #define QM_I2C_IC_INTR_MASK_TX_OVER BIT(3)
974 #define QM_I2C_IC_INTR_MASK_TX_EMPTY BIT(4)
975 #define QM_I2C_IC_INTR_MASK_RD_REQ BIT(5)
976 #define QM_I2C_IC_INTR_MASK_TX_ABORT BIT(6)
977 #define QM_I2C_IC_INTR_MASK_RX_DONE BIT(7)
978 #define QM_I2C_IC_INTR_MASK_ACTIVITY BIT(8)
979 #define QM_I2C_IC_INTR_MASK_STOP_DETECTED BIT(9)
980 #define QM_I2C_IC_INTR_MASK_START_DETECTED BIT(10)
981 #define QM_I2C_IC_INTR_MASK_GEN_CALL_DETECTED BIT(11)
982 #define QM_I2C_IC_INTR_MASK_RESTART_DETECTED BIT(12)
983 #define QM_I2C_IC_INTR_STAT_RX_UNDER BIT(0)
984 #define QM_I2C_IC_INTR_STAT_RX_OVER BIT(1)
985 #define QM_I2C_IC_INTR_STAT_RX_FULL BIT(2)
986 #define QM_I2C_IC_INTR_STAT_TX_OVER BIT(3)
987 #define QM_I2C_IC_INTR_STAT_TX_EMPTY BIT(4)
988 #define QM_I2C_IC_INTR_STAT_RD_REQ BIT(5)
989 #define QM_I2C_IC_INTR_STAT_TX_ABRT BIT(6)
990 #define QM_I2C_IC_INTR_STAT_RX_DONE BIT(7)
991 #define QM_I2C_IC_INTR_STAT_STOP_DETECTED BIT(9)
992 #define QM_I2C_IC_INTR_STAT_START_DETECTED BIT(10)
993 #define QM_I2C_IC_INTR_STAT_GEN_CALL_DETECTED BIT(11)
994 #define QM_I2C_IC_LCNT_MAX (65525)
995 #define QM_I2C_IC_LCNT_MIN (8)
996 #define QM_I2C_IC_HCNT_MAX (65525)
997 #define QM_I2C_IC_HCNT_MIN (6)
998 #define QM_I2C_IC_TAR_MASK (0x3FF)
1000 #define QM_I2C_FIFO_SIZE (16)
1003 #define QM_I2C_IC_DMA_CR_RX_ENABLE BIT(0)
1004 #define QM_I2C_IC_DMA_CR_TX_ENABLE BIT(1)
1020 QM_RW uint32_t reserved[10];
1030 QM_RW uint32_t reserved1[3];
1039 #define qm_gpio_context_t uint8_t
1041 #define QM_NUM_GPIO_PINS (25)
1047 #define QM_GPIO test_gpio
1051 #define QM_GPIO_BASE (0xB0000C00)
1055 #define QM_GPIO qm_gpio
1090 #define QM_ADC ((qm_adc_reg_t *)(&test_adc))
1093 #define QM_ADC ((qm_adc_reg_t *)QM_ADC_BASE)
1096 #define QM_ADC_BASE (0xB0004000)
1099 #define QM_ADC_DIV_MAX (1023)
1100 #define QM_ADC_DELAY_MAX (0x1FFF)
1101 #define QM_ADC_CAL_MAX (0x3F)
1102 #define QM_ADC_FIFO_LEN (32)
1103 #define QM_ADC_FIFO_CLEAR (0xFFFFFFFF)
1105 #define QM_ADC_CAL_SEQ_TABLE_DEFAULT (0x80808080)
1107 #define QM_ADC_CMD_SW_OFFSET (24)
1108 #define QM_ADC_CMD_SW_MASK (0xFF000000)
1109 #define QM_ADC_CMD_CAL_DATA_OFFSET (16)
1110 #define QM_ADC_CMD_RESOLUTION_OFFSET (14)
1111 #define QM_ADC_CMD_RESOLUTION_MASK (0xC000)
1112 #define QM_ADC_CMD_NS_OFFSET (4)
1113 #define QM_ADC_CMD_NS_MASK (0x1F0)
1114 #define QM_ADC_CMD_IE_OFFSET (3)
1115 #define QM_ADC_CMD_IE BIT(3)
1117 #define QM_ADC_INTR_ENABLE_CC BIT(0)
1118 #define QM_ADC_INTR_ENABLE_FO BIT(1)
1119 #define QM_ADC_INTR_ENABLE_CONT_CC BIT(2)
1121 #define QM_ADC_INTR_STATUS_CC BIT(0)
1122 #define QM_ADC_INTR_STATUS_FO BIT(1)
1123 #define QM_ADC_INTR_STATUS_CONT_CC BIT(2)
1125 #define QM_ADC_OP_MODE_IE BIT(27)
1126 #define QM_ADC_OP_MODE_DELAY_OFFSET (0x3)
1127 #define QM_ADC_OP_MODE_DELAY_MASK (0xFFF8)
1128 #define QM_ADC_OP_MODE_OM_MASK (0x7)
1137 #define NUM_FLASH_CONTROLLERS (1)
1138 #define HAS_FLASH_WRITE_DISABLE (1)
1152 QM_RW uint32_t fpr_rd_cfg[4];
1159 #define qm_flash_context_t uint8_t
1161 #define QM_FLASH_REGION_DATA_0_SIZE (0x1000)
1162 #define QM_FLASH_REGION_DATA_0_PAGES (0x02)
1167 uint8_t test_flash_page[0x800];
1169 #define QM_FLASH test_flash
1171 #define QM_FLASH_REGION_DATA_0_BASE (test_flash_page)
1172 #define QM_FLASH_REGION_SYS_0_BASE (test_flash_page)
1173 #define QM_FLASH_REGION_OTP_0_BASE (test_flash_page)
1175 #define QM_FLASH_PAGE_MASK (0xCFF)
1176 #define QM_FLASH_MAX_ADDR (0xFFFFFFFF)
1180 #define QM_FLASH_REGION_DATA_0_BASE (0x00200000)
1181 #define QM_FLASH_REGION_SYS_0_BASE (0x00180000)
1182 #define QM_FLASH_REGION_OTP_0_BASE (0x00000000)
1184 #define QM_FLASH_PAGE_MASK (0xF800)
1185 #define QM_FLASH_MAX_ADDR (0x8000)
1188 #define QM_FLASH_BASE_0 (0xB0100000)
1192 #define QM_FLASH qm_flash
1196 #define QM_FLASH_REGION_DATA_BASE_OFFSET (0x04)
1197 #define QM_FLASH_MAX_WAIT_STATES (0xF)
1198 #define QM_FLASH_MAX_US_COUNT (0x3F)
1199 #define QM_FLASH_MAX_PAGE_NUM \
1200 (QM_FLASH_MAX_ADDR / (4 * QM_FLASH_PAGE_SIZE_DWORDS))
1201 #define QM_FLASH_CLK_SLOW BIT(14)
1202 #define QM_FLASH_LVE_MODE BIT(5)
1205 #define QM_FLASH_TMG_DEF_MASK (0xFFFFFC00)
1207 #define QM_FLASH_MICRO_SEC_COUNT_MASK (0x3F)
1209 #define QM_FLASH_WAIT_STATE_MASK (0x3C0)
1211 #define QM_FLASH_WAIT_STATE_OFFSET (6)
1213 #define QM_FLASH_WRITE_DISABLE_OFFSET (4)
1215 #define QM_FLASH_WRITE_DISABLE_VAL BIT(4)
1218 #define ER_REQ BIT(1)
1224 #define WR_DONE BIT(1)
1227 #define WR_ADDR_OFFSET (2)
1229 #define MASS_ERASE_INFO BIT(6)
1231 #define MASS_ERASE BIT(7)
1234 #define ROM_RD_DIS_U BIT(3)
1236 #define ROM_RD_DIS_L BIT(2)
1238 #define QM_FLASH_CTRL_PRE_FLUSH_MASK BIT(1)
1240 #define QM_FLASH_CTRL_PRE_EN_MASK BIT(0)
1242 #define QM_FLASH_ADDRESS_MASK (0x7FF)
1244 #define QM_FLASH_ADDR_INC (0x10)
1247 #define QM_FLASH_PAGE_SIZE_DWORDS (0x200)
1249 #define QM_FLASH_PAGE_SIZE_BYTES (0x800)
1251 #define QM_FLASH_PAGE_SIZE_BITS (11)
1253 #define QM_FLASH_STTS_ROM_PROG (BIT(2))
1273 #define qm_fpr_context_t uint8_t
1276 #define QM_FPR_GRANULARITY (1024)
1296 QM_RW uint32_t mpr_cfg[4];
1301 #define qm_mpr_context_t uint8_t
1304 #define QM_MPR_GRANULARITY (1024)
1309 #define QM_MPR ((qm_mpr_reg_t *)(&test_mpr))
1313 #define QM_MPR_BASE (0xB0400000)
1314 #define QM_MPR ((qm_mpr_reg_t *)QM_MPR_BASE)
1318 #define QM_MPR_UP_BOUND_OFFSET (10)
1319 #define QM_MPR_WR_EN_OFFSET (20)
1320 #define QM_MPR_WR_EN_MASK 0x700000
1321 #define QM_MPR_RD_EN_OFFSET (24)
1322 #define QM_MPR_RD_EN_MASK 0x7000000
1323 #define QM_MPR_EN_LOCK_OFFSET (30)
1324 #define QM_MPR_EN_LOCK_MASK 0xC0000000
1325 #define QM_MPR_VSTS_VALID BIT(31)
1337 QM_RW uint32_t pad[3];
1348 #define qm_pic_timer_context_t uint8_t
1352 #define QM_PIC_TIMER ((qm_pic_timer_reg_t *)(&test_pic_timer))
1356 #define QM_PIC_TIMER_BASE (0xFEE00320)
1357 #define QM_PIC_TIMER ((qm_pic_timer_reg_t *)QM_PIC_TIMER_BASE)
1394 #define CLK_EXTERN_DIV_DEF_MASK (0xFFFFFFE3)
1395 #define CLK_SYS_CLK_DIV_DEF_MASK (0xFFFFF87F)
1396 #define CLK_RTC_DIV_DEF_MASK (0xFFFFFF83)
1397 #define CLK_GPIO_DB_DIV_DEF_MASK (0xFFFFFFE1)
1398 #define CLK_ADC_DIV_DEF_MASK (0xFC00FFFF)
1399 #define CLK_PERIPH_DIV_DEF_MASK (0xFFFFFFF9)
1411 QM_RW uint32_t pad[3];
1433 #define qm_irq_context_t uint8_t
1435 #define QM_MVIC_REG_VER (0x01)
1436 #define QM_MVIC_REG_REDTBL (0x10)
1440 #define QM_MVIC ((qm_mvic_reg_t *)(&test_mvic))
1444 #define QM_MVIC_BASE (0xFEE00080)
1445 #define QM_MVIC ((qm_mvic_reg_t *)QM_MVIC_BASE)
1448 #define QM_INT_CONTROLLER QM_MVIC
1451 #if defined(ENABLE_EXTERNAL_ISR_HANDLING)
1452 #define QM_ISR_EOI(vector)
1454 #define QM_ISR_EOI(vector) (QM_INT_CONTROLLER->eoi.reg = 0)
1463 qm_ioapic_reg_t test_ioapic;
1464 #define QM_IOAPIC ((qm_ioapic_reg_t *)(&test_ioapic))
1468 #define QM_IOAPIC_BASE (0xFEC00000)
1469 #define QM_IOAPIC ((qm_ioapic_reg_t *)QM_IOAPIC_BASE)
1532 #define qm_dma_context_t uint8_t
1535 #define QM_DMA_CTL_L_INT_EN_MASK BIT(0)
1536 #define QM_DMA_CTL_L_DST_TR_WIDTH_OFFSET (1)
1537 #define QM_DMA_CTL_L_DST_TR_WIDTH_MASK (0x7 << QM_DMA_CTL_L_DST_TR_WIDTH_OFFSET)
1538 #define QM_DMA_CTL_L_SRC_TR_WIDTH_OFFSET (4)
1539 #define QM_DMA_CTL_L_SRC_TR_WIDTH_MASK (0x7 << QM_DMA_CTL_L_SRC_TR_WIDTH_OFFSET)
1540 #define QM_DMA_CTL_L_DINC_OFFSET (7)
1541 #define QM_DMA_CTL_L_DINC_MASK (0x3 << QM_DMA_CTL_L_DINC_OFFSET)
1542 #define QM_DMA_CTL_L_SINC_OFFSET (9)
1543 #define QM_DMA_CTL_L_SINC_MASK (0x3 << QM_DMA_CTL_L_SINC_OFFSET)
1544 #define QM_DMA_CTL_L_DEST_MSIZE_OFFSET (11)
1545 #define QM_DMA_CTL_L_DEST_MSIZE_MASK (0x7 << QM_DMA_CTL_L_DEST_MSIZE_OFFSET)
1546 #define QM_DMA_CTL_L_SRC_MSIZE_OFFSET (14)
1547 #define QM_DMA_CTL_L_SRC_MSIZE_MASK (0x7 << QM_DMA_CTL_L_SRC_MSIZE_OFFSET)
1548 #define QM_DMA_CTL_L_TT_FC_OFFSET (20)
1549 #define QM_DMA_CTL_L_TT_FC_MASK (0x7 << QM_DMA_CTL_L_TT_FC_OFFSET)
1550 #define QM_DMA_CTL_L_LLP_DST_EN_MASK BIT(27)
1551 #define QM_DMA_CTL_L_LLP_SRC_EN_MASK BIT(28)
1552 #define QM_DMA_CTL_H_BLOCK_TS_OFFSET (0)
1553 #define QM_DMA_CTL_H_BLOCK_TS_MASK (0xfff << QM_DMA_CTL_H_BLOCK_TS_OFFSET)
1554 #define QM_DMA_CTL_H_BLOCK_TS_MAX 4095
1555 #define QM_DMA_CTL_H_BLOCK_TS_MIN 1
1558 #define QM_DMA_CFG_L_CH_SUSP_MASK BIT(8)
1559 #define QM_DMA_CFG_L_FIFO_EMPTY_MASK BIT(9)
1560 #define QM_DMA_CFG_L_HS_SEL_DST_OFFSET 10
1561 #define QM_DMA_CFG_L_HS_SEL_DST_MASK BIT(QM_DMA_CFG_L_HS_SEL_DST_OFFSET)
1562 #define QM_DMA_CFG_L_HS_SEL_SRC_OFFSET 11
1563 #define QM_DMA_CFG_L_HS_SEL_SRC_MASK BIT(QM_DMA_CFG_L_HS_SEL_SRC_OFFSET)
1564 #define QM_DMA_CFG_L_DST_HS_POL_OFFSET 18
1565 #define QM_DMA_CFG_L_DST_HS_POL_MASK BIT(QM_DMA_CFG_L_DST_HS_POL_OFFSET)
1566 #define QM_DMA_CFG_L_SRC_HS_POL_OFFSET 19
1567 #define QM_DMA_CFG_L_SRC_HS_POL_MASK BIT(QM_DMA_CFG_L_SRC_HS_POL_OFFSET)
1568 #define QM_DMA_CFG_L_RELOAD_SRC_MASK BIT(30)
1569 #define QM_DMA_CFG_L_RELOAD_DST_MASK BIT(31)
1570 #define QM_DMA_CFG_H_DS_UPD_EN_OFFSET (5)
1571 #define QM_DMA_CFG_H_DS_UPD_EN_MASK BIT(QM_DMA_CFG_H_DS_UPD_EN_OFFSET)
1572 #define QM_DMA_CFG_H_SS_UPD_EN_OFFSET (6)
1573 #define QM_DMA_CFG_H_SS_UPD_EN_MASK BIT(QM_DMA_CFG_H_SS_UPD_EN_OFFSET)
1574 #define QM_DMA_CFG_H_SRC_PER_OFFSET (7)
1575 #define QM_DMA_CFG_H_SRC_PER_MASK (0xf << QM_DMA_CFG_H_SRC_PER_OFFSET)
1576 #define QM_DMA_CFG_H_DEST_PER_OFFSET (11)
1577 #define QM_DMA_CFG_H_DEST_PER_MASK (0xf << QM_DMA_CFG_H_DEST_PER_OFFSET)
1579 #define QM_DMA_ENABLE_CLOCK(dma) \
1580 (QM_SCSS_CCU->ccu_mlayer_ahb_ctl |= QM_CCU_DMA_CLK_EN)
1629 #define QM_DMA_INT_STATUS_TFR BIT(0)
1630 #define QM_DMA_INT_STATUS_BLOCK BIT(1)
1631 #define QM_DMA_INT_STATUS_ERR BIT(4)
1643 QM_RW uint32_t reserved[4];
1647 #define QM_DMA_MISC_CHAN_EN_WE_OFFSET (8)
1650 #define QM_DMA_MISC_CFG_DMA_EN BIT(0)
1655 QM_RW uint32_t reserved[12];
1662 #define QM_DMA test_dma
1664 #define QM_DMA_BASE (0xB0700000)
1666 #define QM_DMA qm_dma
1689 uint32_t test_rom_version;
1690 #define ROM_VERSION_ADDRESS &test_rom_version;
1692 #define ROM_VERSION_ADDRESS \
1693 (BL_DATA_FLASH_REGION_BASE + \
1694 (BL_DATA_SECTION_BASE_PAGE * QM_FLASH_PAGE_SIZE_BYTES) + \
1695 sizeof(qm_flash_data_trim_t))
QM_RW uint32_t gpio_inten
Interrupt Enable.
QM_RW uint32_t flash_stts
FLASH_STTS.
QM_RW uint32_t src_sg_high
SGR.
QM_RW uint32_t de_en
Driver Output Enable Register.
QM_RW mvic_reg_pad_t eoi
End of interrupt.
QM_RW uint32_t ic_fs_spklen
SS and FS Spike Suppression Limit.
QM_RW uint32_t cfg_low
CFG.
QM_RW uint32_t aonpt_ctrl
Always-on periodic timer control.
QM_RW uint32_t ic_status
Status.
QM_RW uint32_t cotps
Code OTP Size Register.
QM_RW uint32_t ccu_sys_clk_ctl
System Clock Control Register.
QM_RW uint32_t osc1_stat0
RTC Oscillator status 0.
QM_RW uint32_t wdt_torr
Timeout Range Register.
QM_RW uint32_t dst_stat_addr_low
DSTATAR.
DMA interrupt register map.
QM_RW uint32_t tar
Transmit Address Register.
QM_RW uint32_t adc_fifo_count
ADC FIFO Count Register.
QM_RW uint32_t intstatus
Interrupt Status.
QM_RW uint32_t ctrl_low
CTL.
QM_RW uint32_t dmardlr
DMA Receive Data Level.
QM_RW uint32_t isr
Interrupt Status Register.
QM_RW uint32_t ccu_mlayer_ahb_ctl
AHB Control Register.
QM_RW uint32_t ic_hs_scl_hcnt
High Speed I2C Clock SCL High Count.
QM_RW uint32_t wdt_comp_version
Component Version Register.
QM_RW uint32_t txftlr
Transmit FIFO Threshold Level.
QM_RW uint32_t adc_seq6
ADC Channel Sequence Table Entry 6.
QM_RW uint32_t rx_sample_dly
RX Sample Delay Register.
QM_RW uint32_t raw_src_trans_low
RawSrcTran.
QM_RW uint32_t gp2
General Purpose Scratchpad Register 2.
QM_RW uint32_t dmacr
DMA Control Register.
QM_RW uint32_t adc_op_mode
ADC Operating Mode Register.
QM_RW uint32_t ic_intr_stat
Interrupt Status.
QM_RW uint32_t ic_comp_param_1
Configuration Parameters.
QM_RW uint32_t id
Identification Register.
QM_RW uint32_t osc0_cfg0
Hybrid Oscillator Configuration 0.
QM_RW uint32_t dar_high
DAR.
QM_RW uint32_t src_stat_low
SSTAT.
QM_RW uint32_t status_src_trans_low
StatusSrcTran.
QM_RW uint32_t mask_tfr_high
MaskTfr.
QM_RW uint32_t adc_seq3
ADC Channel Sequence Table Entry 3.
QM_RW uint32_t raw_block_low
RawBlock.
GPIO Debounce Clock Enable.
QM_RW uint32_t ic_clr_intr
Clear Combined and Individual Interrupt.
QM_RW uint32_t status_err_high
StatusErr.
QM_RW uint32_t clear_dst_trans_high
ClearDstTran.
QM_RW uint32_t rtc_clr
Counter Load Register.
QM_RW uint32_t wake_mask
Wake Mask register.
QM_RW uint32_t ctrlr1
Control Register 1.
QM_RW uint32_t adc_intr_status
ADC Interrupt Status Register.
QM_RW uint32_t ic_clr_rx_under
Clear RX_UNDER Interrupt.
QM_RW uint32_t baudr
Baud Rate Select.
QM_RW uint32_t gpio_config_reg2
GPIO Configuration Register 2.
QM_RW uint32_t ic_hs_spklen
HS spike suppression limit.
QM_RW uint32_t soc_ctrl_lock
SoC Control Register Lock.
QM_RW uint32_t gpio_config_reg1
GPIO Configuration Register 1.
QM_RW uint32_t gp1
General Purpose Scratchpad Register 1.
QM_RW uint32_t ic_clr_rx_over
Clear RX_OVER Interrupt.
QM_RW uint32_t mpr_vdata
MPR_VDATA.
PIC timer register structure.
QM_RW uint32_t adc_seq1
ADC Channel Sequence Table Entry 1.
QM_RW uint32_t fs
Flash Size Register.
QM_RW uint32_t raw_tfr_low
RawTfr.
QM_RW uint32_t ic_ss_scl_lcnt
Standard Speed Clock SCL Low Count.
QM_RW uint32_t ic_sda_setup
SDA Setup.
QM_RW uint32_t status_block_high
StatusBlock.
QM_RW uint32_t rtc_ccr
Counter Control Register.
QM_RW uint32_t src_stat_addr_high
SSTATAR.
qm_adc_t
Number of ADC controllers.
QM_RW uint32_t dlf
Divisor Latch Fraction.
QM_RW uint32_t cfg_high
DmaCfgReg.
QM_RW uint32_t lcr
Line Control.
qm_flash_t
Number of Flash controllers.
QM_RW uint32_t cmp_ref_sel
Comparator reference select.
QM_RW uint32_t ic_enable
Enable.
QM_RW uint32_t ic_dma_rdlr
I2C Receive Data Level Register.
QM_RW uint32_t flash_wr_ctrl
FLASH_WR_CTRL.
QM_RW mvic_reg_pad_t sivr
Spurious vector.
QM_RW uint32_t raw_err_low
RawErr.
QM_RW uint32_t status_tfr_high
StatusTfr.
QM_RW uint32_t ssienr
SSI Enable Register.
QM_RW uint32_t mcr
MODEM Control.
QM_RW uint32_t gpio_swporta_ddr
Port A Data Direction.
QM_RW uint32_t ic_clr_rx_done
Clear RX_DONE Interrupt.
QM_RW uint32_t ic_tx_tl
Transmit FIFO Threshold Level.
QM_RW uint32_t ic_fs_scl_lcnt
Fast Speed I2C Clock SCL Low Count.
Number of Memory Protection Regions.
QM_RW uint32_t dst_stat_low
DSTAT.
QM_RW uint32_t wo_sp
Write-One-to-Set Scratchpad Register.
QM_RW uint32_t status_dst_trans_low
StatusDstTran.
QM_RW uint32_t ic_clr_tx_abrt
Clear TX_ABRT Interrupt.
QM_RW uint32_t cfg_lock
Configuration Lock.
QM_RW uint32_t ic_data_cmd
Data Buffer and Command.
QM_RW uint32_t mask_src_trans_low
MaskSrcTran.
QM_RW uint32_t ic_clr_stop_det
Clear STOP_DET Interrupt.
Quark D2000 peripherals Enable.
QM_RW uint32_t txoicr
Tx FIFO Overflow Interrupt Clear Register.
DMA channel id for channel 1.
QM_RW uint32_t adc_calibration
ADC Calibration Data Register.
QM_RW uint32_t rsts
Reset Status.
QM_RW uint32_t re_en
Receiver Output Enable Register.
QM_RW uint32_t mask_dst_trans_high
MaskDstTran.
QM_RW uint32_t mpr_vdata
MPR Violation Data Value Register.
QM_RW uint32_t mask_err_low
MaskErr.
QM_RW uint32_t det
Driver Output Enable Timing Register.
qm_uart_t
Number of UART controllers.
Memory Protection Region 0.
Memory Protection Region 3.
QM_RW uint32_t aonc_cnt
Always-on counter register.
QM_RW uint32_t rbr_thr_dll
Rx Buffer/ Tx Holding/ Div Latch Low.
QM_RW uint32_t gpio_debounce
Debounce Enable.
QM_RW uint32_t clear_tfr_low
ClearTfr.
QM_RW uint32_t rtc_stat
Interrupt Status Register.
QM_RW uint32_t gps3
General Purpose Sticky Register 3.
QM_RW uint32_t ccu_gpio_db_clk_ctl
Peripheral Clock Divider Control 1.
QM_RW uint32_t mask_tfr_low
MaskTfr.
QM_RW uint32_t loadcount
Load Coun.t.
QM_RW uint32_t raw_dst_trans_high
RawDstTran.
Peripheral Clock Gate Enable.
QM_RW uint32_t pmux_slew_lock
Pin Mux Slew Rate Lock.
QM_RW uint32_t gpio_swporta_dr
Port A Data.
QM_RW uint32_t mask_block_high
MaskBlock.
QM_RW uint32_t p_sts
Processor Status.
QM_RW mvic_reg_pad_t isr
In-service.
QM_RW uint32_t osc_lock_0
Clocks Lock Register.
QM_RW uint32_t status_src_trans_high
StatusSrcTran.
qm_spi_reg_t * qm_spi_controllers[QM_SPI_NUM]
Extern qm_spi_reg_t* array declared at qm_soc_regs.h .
QM_RW uint32_t rar
Receive Address Register.
QM_RW uint32_t ic_rxflr
Receive FIFO Level.
QM_RW uint32_t wdt_comp_type
Component Type Register.
PWM / Timer register map.
QM_RW uint32_t mwcr
Microwire Control Register.
QM_RW uint32_t osc0_stat1
Hybrid Oscillator status 1.
QM_RW uint32_t ic_clr_tx_over
Clear TX_OVER Interrupt.
QM_RW uint32_t src_sg_low
SGR.
QM_RW uint32_t ic_raw_intr_stat
Raw Interrupt Status.
SPI Master 0 Clock Enable.
QM_RW uint32_t clear_block_low
ClearBlock.
QM_RW uint32_t aon_vr
AON Voltage Regulator.
QM_RW uint32_t aonpt_cnt
Always-on periodic timer.
QM_RW uint32_t src_stat_high
SSTAT.
DMA miscellaneous register map.
QM_RW uint32_t rtc_rstat
Interrupt Raw Status Register.
Information register map.
QM_RW uint32_t gpio_intstatus
Interrupt Status.
QM_RW uint32_t clear_dst_trans_low
ClearDstTran.
QM_RW uint32_t dst_stat_addr_high
DSTATAR.
QM_RW pic_timer_reg_pad_t timer_icr
Initial Count Register.
QM_RW uint32_t tmg_ctrl
TMG_CTRL.
QM_RW uint32_t adc_seq7
ADC Channel Sequence Table Entry 7.
System Core register map.
QM_RW uint32_t pm_wait
Power Management Wait.
QM_RW uint32_t id_low
DmaIdReg.
QM_RW uint32_t clear_tfr_high
ClearTfr.
QM_RW uint32_t dst_sg_high
DSR.
QM_RW uint32_t rtc_ccvr
Current Counter Value Register.
QM_RW uint32_t dmasa
DMA Software Acknowledge.
QM_RW uint32_t cmp_pwr
Comparator power enable register.
QM_RW uint32_t src_stat_addr_low
SSTATAR.
Always-on Counter Controller register map.
QM_RW mvic_reg_pad_t icr
Timer initial count.
QM_RW uint32_t rtc_comp_version
End of Interrupt Register.
QM_RW uint32_t rom_wr_data
ROM_WR_DATA.
QM_RW uint32_t cmp_stat_clr
Comparator clear register.
QM_RW uint32_t lcr_ext
Line Extended Control Register.
QM_RW uint32_t adc_seq0
ADC Channel Sequence Table Entry 0.
QM_RW uint32_t wdt_comp_param_2
Component Parameters.
QM_RW uint32_t ic_sda_hold
SDA Hold.
General Purpose register map.
QM_RW uint32_t rom_wr_ctrl
ROM_WR_CTRL.
QM_RW uint32_t rtc_eoi
End of Interrupt Register.
QM_RW uint32_t mask_err_high
MaskErr.
QM_RW uint32_t ccu_lp_clk_ctl
System Low Power Clock Control.
QM_RW uint32_t rxflr
Receive FIFO Level Register.
QM_RW uint32_t tcr
Transceiver Control Register.
QM_RW uint32_t ic_dma_cr
SDA Setup.
QM_RW uint32_t status_int_high
StatusInt.
QM_RW uint32_t timersintstatus
Timers Interrupt Status.
QM_RW uint32_t llp_low
LLP.
QM_RW uint32_t rxuicr
Rx FIFO Underflow Interrupt Clear Register.
QM_RW uint32_t chan_en_low
ChEnReg.
QM_RW uint32_t cfg_low
DmaCfgReg.
qm_spi_t
Number of SPI controllers.
QM_RW uint32_t risr
Raw Interrupt Status Register.
QM_RW uint32_t ic_fs_scl_hcnt
Fast Speed Clock SCL High Count.
QM_RW uint32_t currentvalue
Current Value.
QM_RW uint32_t gpio_ext_porta
Port A External Port.
QM_RW uint32_t adc_sample
ADC Sample Register.
QM_RW uint32_t timersrawintstatus
Timers Raw Interrupt Status.
QM_RW uint32_t htx
Halt Transmission.
qm_rtc_t
Number of RTC controllers.
QM_RW mvic_reg_pad_t ppr
Processor priority.
QM_RW uint32_t osc0_cfg1
Hybrid Oscillator configuration 1.
QM_RW uint32_t lsr
Line Status.
QM_RW uint32_t ccu_ext_clock_ctl
External Clock Control Register.
QM_RW uint32_t id_high
DmaIdReg.
QM_RW uint32_t ic_comp_type
Component Type.
QM_RW pic_timer_reg_pad_t lvttimer
Local Vector Table Timer.
QM_RW uint32_t mask_block_low
MaskBlock.
QM_RW uint32_t rtc_cmr
Current Match Register.
QM_RW uint32_t ic_clr_start_det
Clear START_DET Interrupt.
QM_RW uint32_t gpio_intmask
Interrupt Mask.
QM_RW mvic_reg_pad_t lvttimer
Timer vector.
QM_RW uint32_t soc_ctrl
SoC Control Register.
QM_RW uint32_t aonpt_stat
Always-on periodic timer status register.
QM_RW uint32_t ssi_comp_version
coreKit Version ID register.
QM_RW uint32_t wdt_comp_param_1
Component Parameters Register 1.
QM_RW uint32_t adc_intr_enable
ADC Interrupt Enable Register.
QM_RW uint32_t wo_st
Write-One-to-Set Sticky Scratchpad Register.
QM_RW uint32_t mpr_vsts
Protection Status Register.
QM_RW uint32_t ctrl_high
CTL.
QM_RW uint32_t msticr
Multi-Master Interrupt Clear Register.
QM_RW uint32_t raw_block_high
RawBlock.
QM_RW uint32_t wdt_eoi
Interrupt Clear Register.
qm_gpio_reg_t * qm_gpio[QM_GPIO_NUM]
GPIO register block.
QM_RW uint32_t gpio_int_polarity
Interrupt Polarity.
QM_RW uint32_t raw_dst_trans_low
RawDstTran.
QM_RW uint32_t wdt_crr
Current Restart Register.
QM_RW uint32_t gp3
General Purpose Scratchpad Register 3.
QM_RW uint32_t ic_ss_scl_hcnt
Standard Speed Clock SCL High Count.
QM_RW uint32_t wdt_cr
Control Register.
QM_RW uint32_t ic_clr_activity
Clear ACTIVITY Interrupt.
QM_RW uint32_t wdt_comp_param_4
Component Parameters.
QM_RW uint32_t status_err_low
StatusErr.
QM_RW uint32_t ier_dlh
Interrupt Enable / Divisor Latch High.
QM_RW uint32_t ic_dma_tdlr
DMA Transmit Data Level Register.
QM_RW uint32_t aonpt_cfg
Always-on periodic timer configuration register.
QM_RW uint32_t flash_wr_data
FLASH_WR_DATA.
QM_RW uint32_t gps0
General Purpose Sticky Register 0.
QM_RW uint32_t idr
Identification Register.
QM_RW uint32_t mpr_wr_cfg
Flash Write Protection Control Register.
QM_RW uint32_t ic_sar
Slave Address.
QM_RW uint32_t ic_hs_maddr
High Speed Master ID.
Number of DMA controllers.
DMA channel id for channel 0.
I2C Master 0 Clock Gate Enable.
QM_RW uint32_t pmux_sel_0_lock
Pin Mux Select Lock 0.
QM_RW uint32_t sr
Status Register.
QM_RW uint32_t dst_stat_high
DSTAT.
SPI Slave Clock Gate Enable.
QM_RW uint32_t sar_low
SAR.
QM_RW uint32_t clear_block_high
ClearBlock.
QM_RW uint32_t gpio_porta_eoi
Clear Interrupt.
QM_RW uint32_t ic_clr_gen_call
Clear GEN_CALL Interrupt.
I2C Master 0 Clock Enable.
QM_RW uint32_t raw_src_trans_high
RawSrcTran.
QM_RW uint32_t dar_low
DAR.
QM_RW uint32_t imr
Interrupt Mask Register.
QM_RW uint32_t controlreg
Control.
QM_RW uint32_t timerscompversion
Timers Component Version.
QM_RW mvic_reg_pad_t ccr
Timer current count.
QM_RW uint32_t usr
UART Status.
QM_RW uint32_t adc_seq2
ADC Channel Sequence Table Entry 2.
Memory Protection Region 2.
QM_RW uint32_t wdt_ccvr
Current Counter Value Register.
QM_RW uint32_t cfg_high
CFG.
QM_RW pic_timer_reg_pad_t timer_ccr
Current Count Register.
QM_RW uint32_t status_tfr_low
StatusTfr.
QM_RW uint32_t chan_en_high
ChEnReg.
QM_RW uint32_t rxoicr
Rx FIFO Overflow Interrupt Clear Register.
QM_RW uint32_t dotps
Data OTP Size Register.
QM_RW uint32_t adc_seq5
ADC Channel Sequence Table Entry 5.
QM_RW uint32_t mpr_vsts
MPR_VSTS.
QM_RW uint32_t dst_sg_low
DSR.
QM_RW uint32_t ser
Slave Enable Register.
QM_RW uint32_t clear_err_high
ClearErr.
SPI Master 0 Clock Gate Enable.
QM_RW uint32_t iir_fcr
Interrupt Identification / FIFO Control.
QM_RW uint32_t ic_intr_mask
Interrupt Mask.
QM_RW uint32_t raw_tfr_high
RawTfr.
qm_gpio_t
Number of GPIO controllers.
qm_fpr_id_t
FPR register map.
QM_RW uint32_t adc_seq4
ADC Channel Sequence Table Entry 4.
DMA channel register map.
qm_i2c_t
Number of I2C controllers.
QM_RW uint32_t gpio_ls_sync
Synchronization Level.
QM_RW uint32_t pmux_in_en_lock
Pin Mux Slew Rate Lock.
QM_RW uint32_t adc_cmd
ADC Command Register.
qm_i2c_reg_t * qm_i2c[QM_I2C_NUM]
I2C register block.
QM_RW uint32_t ic_tx_abrt_source
Transmit Abort Source.
QM_RW uint32_t cmp_en
Comparator enable.
QM_RW uint32_t rstc
Reset Control.
QM_RW uint32_t eoi
End Of Interrupt.
QM_RW uint32_t ctrlr0
Control Register 0.
QM_RW uint32_t scr
Scratchpad.
QM_RW uint32_t gpio_ver_id_code
GPIO Component Version.
QM_RW uint32_t ccu_periph_clk_div_ctl0
Peripheral Clock Divider Control 0.
Memory Protection Region register map.
QM_RW uint32_t pm_lock
Power Management Lock.
QM_RW uint32_t gps1
General Purpose Sticky Register 1.
QM_RW uint32_t gpio_raw_intstatus
Raw Interrupt Status.
QM_RW uint32_t gpio_inttype_level
Interrupt Type.
QM_RW uint32_t msr
MODEM Status.
qm_pwm_t
Number of PWM / Timer controllers.
QM_RW uint32_t wdt_comp_param_3
Component Parameters.
QM_RW uint32_t rev
Revision Register.
QM_RW uint32_t gps2
General Purpose Sticky Register 2.
QM_RW uint32_t raw_err_high
RawErr.
QM_RW uint32_t ccu_periph_clk_gate_ctl
Peripheral Clock Gate Control.
QM_RW uint32_t status_block_low
StatusBlock.
QM_RW uint32_t tat
TurnAround Timing Register.
QM_RW uint32_t llp_high
LLP.
QM_RW mvic_reg_pad_t irr
Interrupt request.
QM_RW uint32_t wdt_comp_param_5
Component Parameters.
QM_RW uint32_t status_dst_trans_high
StatusDstTran.
Memory Protection Region 1.
QM_RW uint32_t cmp_ref_pol
Comparator reference polarity select register.
QM_RW uint32_t pmux_pullup_lock
Pin Mux Pullup Lock.
qm_dma_channel_id_t
DMA channel IDs.
QM_RW uint32_t ic_hs_scl_lcnt
High Speed I2C Clock SCL Low Count.
clk_periph_t
Peripheral clock register map.
Power Management register map.
QM_RW uint32_t gpio_id_code
GPIO ID code.
QM_RW uint32_t txflr
Transmit FIFO Level Register.
qm_dma_handshake_interface_t
DMA hardware handshake interfaces.
QM_RW uint32_t status_int_low
StatusInt.
QM_RW uint32_t gp0
General Purpose Scratchpad Register 0.
QM_RW mvic_reg_pad_t tpr
Task priority.
QM_RW uint32_t ic_enable_status
Enable Status.
QM_RW uint32_t wdt_stat
Interrupt Status Register.
QM_RW uint32_t test_low
DmaTestReg.
QM_RW uint32_t osc1_cfg0
RTC Oscillator Configuration 0.
PWM / Timer channel register map.
QM_RW uint32_t mask_src_trans_high
MaskSrcTran.
QM_RW uint32_t clear_src_trans_low
ClearSrcTran.
QM_RW uint32_t timerseoi
Timers End Of Interrupt.
qm_wdt_t
Number of WDT controllers.
QM_RW uint32_t mask_dst_trans_low
MaskDstTran.
QM_RW uint32_t dmatdlr
DMA Transmit Data Level.
QM_RW uint32_t ic_con
Control Register.
QM_RW uint32_t ic_comp_version
Component Version.
QM_RW uint32_t ic_tar
Master Target Address.
Watchdog timer register map.
QM_RW uint32_t ic_clr_restart_det
clear the RESTART_DET interrupt.
QM_RW uint32_t ic_rx_tl
Receive FIFO Threshold Level.
QM_RW uint32_t ic_ack_general_call
General Call Ack.
QM_RW uint32_t clear_src_trans_high
ClearSrcTran.
QM_RW uint32_t aonc_cfg
Always-on counter enable.
QM_RW uint32_t rs
RAM Size Register.
Peripheral Registers register map.
QM_RW uint32_t icr
Interrupt Clear Register.
QM_RW uint32_t ic_txflr
Transmit FIFO Level.
QM_RW uint32_t clear_err_low
ClearErr.
QM_RW uint32_t test_high
DmaTestReg.
QM_RW uint32_t periph_cfg0
Peripheral Configuration.
QM_RW uint32_t ic_clr_rd_req
Clear RD_REQ Interrupt.
qm_aonc_t
Number of Always-on counter controllers.
QM_RW uint32_t sar_high
SAR.
QM_RW uint32_t rxftlr
Receive FIFO Threshold Level.
GPIO Interrupt Clock Enable.
QM_RW uint32_t gpio_int_bothedge
Interrupt both edge type.