Intel® Quark™ Microcontroller Software Interface  1.4.0
Intel® Quark™ Microcontroller BSP
qm_ss_isr.h
1 /*
2  * {% copyright %}
3  */
4 
5 #ifndef __QM_SS_ISR_H__
6 #define __QM_SS_ISR_H__
7 
8 #include "qm_common.h"
9 
10 /**
11  * Sensor Subsystem Interrupt Service Routines.
12  *
13  * @defgroup groupSSISR SS ISR
14  * @{
15  */
16 
17 /**
18  * ISR for ADC interrupt.
19  *
20  * This function needs to be registered with
21  * @code qm_ss_irq_request(QM_SS_IRQ_ADC_0_INT, qm_ss_adc_0_isr);
22  * @endcode if IRQ based conversions are used.
23  */
24 QM_ISR_DECLARE(qm_ss_adc_0_isr);
25 
26 /**
27  * ISR for ADC error interrupt.
28  *
29  * This function needs to be registered with
30  * @code qm_ss_irq_request(QM_SS_IRQ_ADC_0_ERROR_INT,
31  * qm_ss_adc_0_error_isr);
32  * @endcode if IRQ based conversions are used.
33  */
34 QM_ISR_DECLARE(qm_ss_adc_0_error_isr);
35 
36 /**
37  * ISR for SS ADC 0 calibration interrupt.
38  *
39  * This function needs to be registered with
40  * @code QM_IRQ_REQUEST(QM_SS_IRQ_ADC_0_CAL_INT, qm_ss_adc_0_cal_isr);
41  * @endcode if IRQ based calibration is used.
42  */
43 QM_ISR_DECLARE(qm_ss_adc_0_cal_isr);
44 
45 /**
46  * ISR for SS ADC 0 mode change interrupt.
47  *
48  * This function needs to be registered with
49  * @code QM_IRQ_REQUEST(QM_SS_IRQ_ADC_0_PWR_INT, qm_ss_adc_0_pwr_isr);
50  * @endcode if IRQ based mode change is used.
51  */
52 QM_ISR_DECLARE(qm_ss_adc_0_pwr_isr);
53 
54 /**
55  * ISR for GPIO 0 error interrupt.
56  *
57  * This function needs to be registered with
58  * @code qm_ss_irq_request(QM_SS_IRQ_GPIO_0_INT, qm_ss_gpio_0_isr);
59  * @endcode if IRQ based transfers are used.
60  */
61 QM_ISR_DECLARE(qm_ss_gpio_0_isr);
62 
63 /**
64  * ISR for GPIO 1 error interrupt.
65  *
66  * This function needs to be registered with
67  * @code qm_ss_irq_request(QM_SS_IRQ_GPIO_1_INT, qm_ss_gpio_1_isr);
68  * @endcode if IRQ based transfers are used.
69  */
70 QM_ISR_DECLARE(qm_ss_gpio_1_isr);
71 
72 /**
73  * ISR for I2C 0 error interrupt.
74  *
75  * This function needs to be registered with
76  * @code qm_ss_irq_request(QM_SS_IRQ_I2C_0_ERROR_INT, qm_ss_i2c_0_error_isr);
77  * @endcode if IRQ based transfers are used.
78  */
79 QM_ISR_DECLARE(qm_ss_i2c_0_error_isr);
80 
81 /**
82  * ISR for I2C 0 RX data available interrupt.
83  * This function needs to be registered with
84  * @code qm_ss_irq_request(QM_SS_IRQ_I2C_0_RX_AVAIL_INT,
85  * qm_ss_i2c_0_rx_avail_isr);
86  * @endcode if IRQ based transfers are used.
87  */
88 QM_ISR_DECLARE(qm_ss_i2c_0_rx_avail_isr);
89 
90 /**
91  * ISR for I2C 0 TX data requested interrupt.
92  * This function needs to be registered with
93  * @code qm_ss_irq_request(QM_SS_IRQ_I2C_0_TX_REQ_INT, qm_ss_i2c_0_tx_req_isr);
94  * @endcode if IRQ based transfers are used.
95  */
96 QM_ISR_DECLARE(qm_ss_i2c_0_tx_req_isr);
97 
98 /**
99  * ISR for I2C 0 STOP detected interrupt.
100  * This function needs to be registered with
101  * @code qm_ss_irq_request(QM_SS_IRQ_I2C_0_STOP_DET_INT,
102  * qm_ss_i2c_0_stop_det_isr);
103  * @endcode if IRQ based transfers are used.
104  */
105 QM_ISR_DECLARE(qm_ss_i2c_0_stop_det_isr);
106 
107 /**
108  * ISR for I2C 1 error interrupt.
109  * This function needs to be registered with
110  * @code qm_ss_irq_request(QM_SS_IRQ_I2C_1_ERROR_INT, qm_ss_i2c_1_error_isr);
111  * @endcode if IRQ based transfers are used.
112  */
113 QM_ISR_DECLARE(qm_ss_i2c_1_error_isr);
114 
115 /**
116  * ISR for I2C 1 RX data available interrupt.
117  * This function needs to be registered with
118  * @code qm_ss_irq_request(QM_SS_IRQ_I2C_1_RX_AVAIL_INT,
119  * qm_ss_i2c_1_rx_avail_isr);
120  * @endcode if IRQ based transfers are used.
121  */
122 QM_ISR_DECLARE(qm_ss_i2c_1_rx_avail_isr);
123 
124 /**
125  * ISR for I2C 1 TX data requested interrupt.
126  * This function needs to be registered with
127  * @code qm_ss_irq_request(QM_SS_IRQ_I2C_1_TX_REQ_INT, qm_ss_i2c_1_tx_req_isr);
128  * @endcode if IRQ based transfers are used.
129  */
130 QM_ISR_DECLARE(qm_ss_i2c_1_tx_req_isr);
131 
132 /**
133  * ISR for I2C 1 STOP detected interrupt.
134  * This function needs to be registered with
135  * @code qm_ss_irq_request(QM_SS_IRQ_I2C_1_STOP_DET_INT,
136  * qm_ss_i2c_1_stop_det_isr);
137  * @endcode if IRQ based transfers are used.
138  */
139 QM_ISR_DECLARE(qm_ss_i2c_1_stop_det_isr);
140 
141 /**
142  * ISR for SPI 0 error interrupt.
143  *
144  * This function needs to be registered with
145  * @code qm_ss_irq_request(QM_SS_IRQ_SPI_0_ERROR_INT,
146  * qm_ss_spi_0_error_isr);
147  * @endcode if IRQ based transfers are used.
148  */
149 QM_ISR_DECLARE(qm_ss_spi_0_error_isr);
150 
151 /**
152  * ISR for SPI 1 error interrupt.
153  *
154  * This function needs to be registered with
155  * @code qm_ss_irq_request(QM_SS_IRQ_SPI_1_ERROR_INT,
156  * qm_ss_spi_1_error_isr);
157  * @endcode if IRQ based transfers are used.
158  */
159 QM_ISR_DECLARE(qm_ss_spi_1_error_isr);
160 
161 /**
162  * ISR for SPI 0 TX data requested interrupt.
163  *
164  * This function needs to be registered with
165  * @code qm_ss_irq_request(QM_SS_IRQ_SPI_0_TX_REQ_INT,
166  * qm_ss_spi_0_tx_req_isr);
167  * @endcode if IRQ based transfers are used.
168  */
169 QM_ISR_DECLARE(qm_ss_spi_0_tx_req_isr);
170 
171 /**
172  * ISR for SPI 1 TX data requested interrupt.
173  *
174  * This function needs to be registered with
175  * @code qm_ss_irq_request(QM_SS_IRQ_SPI_1_TX_REQ_INT,
176  * qm_ss_spi_1_tx_req_isr);
177  * @endcode if IRQ based transfers are used.
178  */
179 QM_ISR_DECLARE(qm_ss_spi_1_tx_req_isr);
180 
181 /**
182  * ISR for SPI 0 RX data available interrupt.
183  *
184  * This function needs to be registered with
185  * @code qm_ss_irq_request(QM_SS_IRQ_SPI_0_RX_AVAIL_INT,
186  * qm_ss_spi_0_rx_avail_isr);
187  * @endcode if IRQ based transfers are used.
188  */
189 QM_ISR_DECLARE(qm_ss_spi_0_rx_avail_isr);
190 
191 /**
192  * ISR for SPI 1 data available interrupt.
193  *
194  * This function needs to be registered with
195  * @code qm_ss_irq_request(QM_SS_IRQ_SPI_1_RX_AVAIL_INT,
196  * qm_ss_spi_1_rx_avail_isr);
197  * @endcode if IRQ based transfers are used.
198  */
199 QM_ISR_DECLARE(qm_ss_spi_1_rx_avail_isr);
200 
201 /**
202  * ISR for SS Timer 0 interrupt.
203  *
204  * This function needs to be registered with
205  * @code qm_ss_int_vector_request(QM_ARC_TIMER_0_INT, qm_ss_timer_0_isr);
206  * @endcode
207  */
208 QM_ISR_DECLARE(qm_ss_timer_0_isr);
209 
210 /**
211  * @}
212  */
213 
214 #endif /* __QM_SS_ISR_H__ */
QM_ISR_DECLARE(qm_ss_adc_0_isr)
ISR for ADC interrupt.
Definition: qm_ss_adc.c:197