Intel® Quark™ Microcontroller Software Interface
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qm_ss_isr.h
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/*
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* {% copyright %}
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*/
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#ifndef __QM_SS_ISR_H__
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#define __QM_SS_ISR_H__
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#include "qm_common.h"
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/**
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* Sensor Subsystem Interrupt Service Routines.
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*
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* @defgroup groupSSISR SS ISR
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* @{
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*/
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/**
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* ISR for ADC interrupt.
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*
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* This function needs to be registered with
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* @code qm_ss_irq_request(QM_SS_IRQ_ADC_0_INT, qm_ss_adc_0_isr);
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* @endcode if IRQ based conversions are used.
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*/
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QM_ISR_DECLARE
(qm_ss_adc_0_isr);
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/**
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* ISR for ADC error interrupt.
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*
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* This function needs to be registered with
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* @code qm_ss_irq_request(QM_SS_IRQ_ADC_0_ERROR_INT,
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* qm_ss_adc_0_error_isr);
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* @endcode if IRQ based conversions are used.
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*/
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QM_ISR_DECLARE
(qm_ss_adc_0_error_isr);
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/**
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* ISR for SS ADC 0 calibration interrupt.
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*
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* This function needs to be registered with
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* @code QM_IRQ_REQUEST(QM_SS_IRQ_ADC_0_CAL_INT, qm_ss_adc_0_cal_isr);
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* @endcode if IRQ based calibration is used.
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*/
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QM_ISR_DECLARE
(qm_ss_adc_0_cal_isr);
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/**
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* ISR for SS ADC 0 mode change interrupt.
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*
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* This function needs to be registered with
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* @code QM_IRQ_REQUEST(QM_SS_IRQ_ADC_0_PWR_INT, qm_ss_adc_0_pwr_isr);
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* @endcode if IRQ based mode change is used.
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*/
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QM_ISR_DECLARE
(qm_ss_adc_0_pwr_isr);
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/**
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* ISR for GPIO 0 error interrupt.
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*
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* This function needs to be registered with
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* @code qm_ss_irq_request(QM_SS_IRQ_GPIO_0_INT, qm_ss_gpio_0_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE
(qm_ss_gpio_0_isr);
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/**
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* ISR for GPIO 1 error interrupt.
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*
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* This function needs to be registered with
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* @code qm_ss_irq_request(QM_SS_IRQ_GPIO_1_INT, qm_ss_gpio_1_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE
(qm_ss_gpio_1_isr);
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/**
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* ISR for I2C 0 error interrupt.
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*
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* This function needs to be registered with
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* @code qm_ss_irq_request(QM_SS_IRQ_I2C_0_ERROR_INT, qm_ss_i2c_0_error_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE
(qm_ss_i2c_0_error_isr);
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/**
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* ISR for I2C 0 RX data available interrupt.
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* This function needs to be registered with
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* @code qm_ss_irq_request(QM_SS_IRQ_I2C_0_RX_AVAIL_INT,
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* qm_ss_i2c_0_rx_avail_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE
(qm_ss_i2c_0_rx_avail_isr);
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/**
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* ISR for I2C 0 TX data requested interrupt.
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* This function needs to be registered with
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* @code qm_ss_irq_request(QM_SS_IRQ_I2C_0_TX_REQ_INT, qm_ss_i2c_0_tx_req_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE
(qm_ss_i2c_0_tx_req_isr);
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/**
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* ISR for I2C 0 STOP detected interrupt.
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* This function needs to be registered with
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* @code qm_ss_irq_request(QM_SS_IRQ_I2C_0_STOP_DET_INT,
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* qm_ss_i2c_0_stop_det_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE
(qm_ss_i2c_0_stop_det_isr);
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/**
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* ISR for I2C 1 error interrupt.
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* This function needs to be registered with
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* @code qm_ss_irq_request(QM_SS_IRQ_I2C_1_ERROR_INT, qm_ss_i2c_1_error_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE
(qm_ss_i2c_1_error_isr);
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/**
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* ISR for I2C 1 RX data available interrupt.
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* This function needs to be registered with
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* @code qm_ss_irq_request(QM_SS_IRQ_I2C_1_RX_AVAIL_INT,
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* qm_ss_i2c_1_rx_avail_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE
(qm_ss_i2c_1_rx_avail_isr);
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/**
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* ISR for I2C 1 TX data requested interrupt.
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* This function needs to be registered with
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* @code qm_ss_irq_request(QM_SS_IRQ_I2C_1_TX_REQ_INT, qm_ss_i2c_1_tx_req_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE
(qm_ss_i2c_1_tx_req_isr);
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/**
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* ISR for I2C 1 STOP detected interrupt.
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* This function needs to be registered with
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* @code qm_ss_irq_request(QM_SS_IRQ_I2C_1_STOP_DET_INT,
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* qm_ss_i2c_1_stop_det_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE
(qm_ss_i2c_1_stop_det_isr);
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/**
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* ISR for SPI 0 error interrupt.
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*
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* This function needs to be registered with
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* @code qm_ss_irq_request(QM_SS_IRQ_SPI_0_ERROR_INT,
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* qm_ss_spi_0_error_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE
(qm_ss_spi_0_error_isr);
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/**
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* ISR for SPI 1 error interrupt.
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*
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* This function needs to be registered with
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* @code qm_ss_irq_request(QM_SS_IRQ_SPI_1_ERROR_INT,
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* qm_ss_spi_1_error_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE
(qm_ss_spi_1_error_isr);
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/**
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* ISR for SPI 0 TX data requested interrupt.
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*
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* This function needs to be registered with
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* @code qm_ss_irq_request(QM_SS_IRQ_SPI_0_TX_REQ_INT,
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* qm_ss_spi_0_tx_req_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE
(qm_ss_spi_0_tx_req_isr);
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/**
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* ISR for SPI 1 TX data requested interrupt.
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*
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* This function needs to be registered with
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* @code qm_ss_irq_request(QM_SS_IRQ_SPI_1_TX_REQ_INT,
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* qm_ss_spi_1_tx_req_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE
(qm_ss_spi_1_tx_req_isr);
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/**
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* ISR for SPI 0 RX data available interrupt.
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*
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* This function needs to be registered with
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* @code qm_ss_irq_request(QM_SS_IRQ_SPI_0_RX_AVAIL_INT,
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* qm_ss_spi_0_rx_avail_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE
(qm_ss_spi_0_rx_avail_isr);
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/**
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* ISR for SPI 1 data available interrupt.
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*
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* This function needs to be registered with
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* @code qm_ss_irq_request(QM_SS_IRQ_SPI_1_RX_AVAIL_INT,
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* qm_ss_spi_1_rx_avail_isr);
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* @endcode if IRQ based transfers are used.
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*/
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QM_ISR_DECLARE
(qm_ss_spi_1_rx_avail_isr);
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/**
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* ISR for SS Timer 0 interrupt.
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*
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* This function needs to be registered with
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* @code qm_ss_int_vector_request(QM_ARC_TIMER_0_INT, qm_ss_timer_0_isr);
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* @endcode
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*/
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QM_ISR_DECLARE
(qm_ss_timer_0_isr);
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/**
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* @}
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*/
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#endif
/* __QM_SS_ISR_H__ */
QM_ISR_DECLARE
QM_ISR_DECLARE(qm_ss_adc_0_isr)
ISR for ADC interrupt.
Definition:
qm_ss_adc.c:197
drivers
include
qm_ss_isr.h
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