5 #include "power_states.h"
9 #include "qm_sensor_regs.h"
11 #include "soc_watch.h"
16 QM_SCSS_PMU->slp_cfg &= ~QM_SCSS_SLP_CFG_LPMODE_EN;
20 QM_SCSS_PMU->pm1c |= QM_SCSS_PM1C_SLPEN;
33 QM_SCSS_PMU->slp_cfg |= QM_SCSS_SLP_CFG_LPMODE_EN;
36 QM_SCSS_PMU->pm1c |= QM_SCSS_PM1C_SLPEN;
39 #if (ENABLE_RESTORE_CONTEXT) && (!QM_SENSOR)
45 extern uint32_t *__x86_restore_info;
51 uint32_t sp_restore_storage;
60 qm_x86_set_resume_vector(sleep_restore_trap, __x86_restore_info);
63 qm_x86_save_context(sp_restore_storage);
77 qm_x86_restore_context(sleep_restore_trap, sp_restore_storage);
88 qm_x86_set_resume_vector(deep_sleep_restore_trap, __x86_restore_info);
91 qm_x86_save_context(sp_restore_storage);
105 qm_x86_restore_context(deep_sleep_restore_trap, sp_restore_storage);
116 qm_x86_set_resume_vector(sleep_restore_trap, __x86_restore_info);
119 qm_x86_save_context(sp_restore_storage);
135 qm_x86_restore_context(sleep_restore_trap, sp_restore_storage);
140 QM_SCSS_GP->gps0 |= BIT(QM_GPS0_BIT_X86_WAKEUP);
156 __asm__ __volatile__(
"sti\n\t"
162 QM_SCSS_CCU->ccu_lp_clk_ctl &= ~QM_SCSS_CCU_C2_LP_EN;
172 QM_SCSS_CCU->ccu_lp_clk_ctl |= QM_SCSS_CCU_C2_LP_EN;
void qm_power_cpu_c1()
Enter Host C1 state.
int vreg_plat3p3_set_mode(const vreg_mode_t mode)
Set Platform 3P3 Voltage Regulator mode.
0x02C Clock Control register.
void qm_power_soc_deep_sleep(const qm_power_wake_event_t wake_event)
Put SoC to deep sleep.
void qm_power_cpu_c2lp()
Enter Host C2LP state or SoC LPSS state.
int vreg_plat1p8_set_mode(const vreg_mode_t mode)
Set Platform 1P8 Voltage Regulator mode.
void qm_power_soc_deep_sleep_restore(void)
Enter SoC deep sleep state and restore after wake up.
void qm_power_soc_sleep(void)
Put SoC to sleep.
0x550 Sleep Configuration.
void qm_power_soc_sleep_restore(void)
Enter SoC sleep state and restore after wake up.
void qm_power_soc_set_x86_restore_flag(void)
Enable the x86 startup restore flag, see GPS0 #define in qm_soc_regs.h.
void qm_power_sleep_wait()
Save context, enter x86 C2 power save state and restore after wake up.
void qm_power_cpu_c2()
Enter Host C2 state or SoC LPSS state.