5 #include "power_states.h"
6 #include "ss_power_states.h"
8 #include "qm_sensor_regs.h"
10 #include "qm_common.h"
32 #define SLEEP_INT_EN BIT(4)
33 #define SLEEP_TIMER_ON (0x0)
34 #define SLEEP_TIMER_OFF (0x20)
35 #define SLEEP_TIMER_RTC_OFF (0x60)
37 #define SS_STATE_1_TIMER_ON (SLEEP_TIMER_ON | SLEEP_INT_EN)
38 #define SS_STATE_1_TIMER_OFF (SLEEP_TIMER_OFF | SLEEP_INT_EN)
39 #define SS_STATE_2 (SLEEP_TIMER_RTC_OFF | SLEEP_INT_EN)
43 uint32_t creg_mst0_ctrl = 0;
45 creg_mst0_ctrl = __builtin_arc_lr(QM_SS_CREG_BASE);
52 creg_mst0_ctrl |= (QM_SS_IO_CREG_MST0_CTRL_ADC_CLK_GATE |
53 QM_SS_IO_CREG_MST0_CTRL_I2C1_CLK_GATE |
54 QM_SS_IO_CREG_MST0_CTRL_I2C0_CLK_GATE |
55 QM_SS_IO_CREG_MST0_CTRL_SPI1_CLK_GATE |
56 QM_SS_IO_CREG_MST0_CTRL_SPI0_CLK_GATE);
58 __builtin_arc_sr(creg_mst0_ctrl, QM_SS_CREG_BASE);
60 QM_SCSS_CCU->ccu_lp_clk_ctl |= QM_SCSS_CCU_SS_LPS_EN;
66 uint32_t creg_mst0_ctrl = 0;
68 creg_mst0_ctrl = __builtin_arc_lr(QM_SS_CREG_BASE);
75 creg_mst0_ctrl &= ~(QM_SS_IO_CREG_MST0_CTRL_ADC_CLK_GATE |
76 QM_SS_IO_CREG_MST0_CTRL_I2C1_CLK_GATE |
77 QM_SS_IO_CREG_MST0_CTRL_I2C0_CLK_GATE |
78 QM_SS_IO_CREG_MST0_CTRL_SPI1_CLK_GATE |
79 QM_SS_IO_CREG_MST0_CTRL_SPI0_CLK_GATE);
81 __builtin_arc_sr(creg_mst0_ctrl, QM_SS_CREG_BASE);
83 QM_SCSS_CCU->ccu_lp_clk_ctl &= ~QM_SCSS_CCU_SS_LPS_EN;
96 (__builtin_arc_lr(QM_SS_AUX_STATUS32) & QM_SS_STATUS32_E_MASK) >> 1;
98 SOC_WATCH_LOG_EVENT(SOCW_ARC_EVENT_SS1, 0);
103 __asm__ __volatile__(
"sleep %0"
105 :
"r"(SS_STATE_1_TIMER_OFF | priority)
110 __asm__ __volatile__(
"sleep %0"
112 :
"r"(SS_STATE_1_TIMER_ON | priority)
127 (__builtin_arc_lr(QM_SS_AUX_STATUS32) & QM_SS_STATUS32_E_MASK) >> 1;
129 SOC_WATCH_LOG_EVENT(SOCW_ARC_EVENT_SS2, 0);
132 __asm__ __volatile__(
"sleep %0"
134 :
"r"(SS_STATE_2 | priority)
138 #if (ENABLE_RESTORE_CONTEXT)
139 extern uint32_t arc_restore_addr;
140 uint32_t cpu_context[33];
149 qm_ss_set_resume_vector(sleep_restore_trap, arc_restore_addr);
152 qm_ss_save_context(cpu_context);
166 qm_ss_restore_context(sleep_restore_trap, cpu_context);
176 qm_ss_set_resume_vector(deep_sleep_restore_trap, arc_restore_addr);
179 qm_ss_save_context(cpu_context);
193 qm_ss_restore_context(deep_sleep_restore_trap, cpu_context);
204 qm_ss_set_resume_vector(sleep_restore_trap, arc_restore_addr);
207 qm_ss_save_context(cpu_context);
223 qm_ss_restore_context(sleep_restore_trap, cpu_context);
228 QM_SCSS_GP->gps0 |= BIT(QM_GPS0_BIT_SENSOR_WAKEUP);
void qm_ss_power_cpu_ss1(const qm_ss_power_cpu_ss1_mode_t mode)
Enter Sensor SS1 state.
void qm_ss_power_cpu_ss2(void)
Enter Sensor SS2 state or SoC LPSS state.
void qm_ss_power_sleep_wait(void)
Save context, enter ARC SS1 power save state and restore after wake up.
void qm_power_soc_set_ss_restore_flag(void)
Enable the SENSOR startup restore flag.
0x02C Clock Control register.
Disable SS Timers in SS1.
void qm_power_soc_deep_sleep(const qm_power_wake_event_t wake_event)
Put SoC to deep sleep.
void qm_ss_power_soc_sleep_restore(void)
Enter SoC sleep state and restore after wake up.
void qm_ss_power_soc_lpss_disable()
Disable LPSS state entry.
qm_ss_power_cpu_ss1_mode_t
Sensor Subsystem SS1 Timers mode type.
Keep SS Timers enabled in SS1.
void qm_ss_power_soc_lpss_enable()
Enable LPSS state entry.
void qm_power_soc_sleep(void)
Put SoC to sleep.
void qm_ss_power_soc_deep_sleep_restore(void)
Enter SoC sleep state and restore after wake up.