Intel® Quark™ Microcontroller Software Interface  1.4.0
Intel® Quark™ Microcontroller BSP
qm_i2c.c
1 /*
2  * {% copyright %}
3  */
4 
5 #include <string.h>
6 #include "qm_i2c.h"
7 #include "clk.h"
8 
9 #define TX_TL (2)
10 #define RX_TL (5)
11 #define SPK_LEN_SS (1)
12 #define SPK_LEN_FS_FSP (2)
13 
14 /* Number of retries before giving up on disabling the controller. */
15 #define I2C_POLL_COUNT (1000000)
16 #define I2C_POLL_MICROSECOND (1)
17 
18 #ifndef UNIT_TEST
19 #if (QUARK_SE)
20 qm_i2c_reg_t *qm_i2c[QM_I2C_NUM] = {(qm_i2c_reg_t *)QM_I2C_0_BASE,
21  (qm_i2c_reg_t *)QM_I2C_1_BASE};
22 #elif(QUARK_D2000)
23 qm_i2c_reg_t *qm_i2c[QM_I2C_NUM] = {(qm_i2c_reg_t *)QM_I2C_0_BASE};
24 #endif
25 #endif
26 
27 static volatile const qm_i2c_transfer_t *i2c_transfer[QM_I2C_NUM];
28 static volatile uint32_t i2c_write_pos[QM_I2C_NUM], i2c_read_pos[QM_I2C_NUM],
29  i2c_read_cmd_send[QM_I2C_NUM];
30 
31 /* True if user buffers have been updated. */
32 static volatile bool transfer_ongoing;
33 static volatile bool first_start;
34 /*
35  * Keep track of activity if addressed.
36  * There is no register which keeps track of the internal state machine status,
37  * whether it is addressed, transmitting or receiving.
38  * The only way to keep track of this is to save the information that the driver
39  * received one the following interrupts:
40  * - General call interrupt
41  * - Read request
42  * - RX FIFO full.
43  * Also, if no interrupt has been received during an RX transaction, the driver
44  * can check the controller has been addressed if data has been effectively
45  * received.
46  */
47 static volatile bool is_addressed = false;
48 
49 /*
50  * I2C DMA controller configuration descriptor.
51  */
52 typedef struct {
53  qm_i2c_t i2c; /* I2C controller. */
54  qm_dma_t dma_controller_id;
55  qm_dma_channel_id_t dma_tx_channel_id; /* TX channel ID. */
56  qm_dma_transfer_t dma_tx_transfer_config; /* Configuration for TX. */
57  qm_dma_channel_id_t dma_rx_channel_id; /* RX channel ID. */
58  qm_dma_transfer_t dma_rx_transfer_config; /* Configuration for RX. */
59  /* Configuration for writing READ commands during an RX operation. */
60  qm_dma_transfer_t dma_cmd_transfer_config;
61  volatile bool ongoing_dma_tx_operation; /* Keep track of ongoing TX. */
62  volatile bool ongoing_dma_rx_operation; /* Keep track of oingoing RX. */
63  int tx_abort_status;
64  int i2c_error_code;
65 } i2c_dma_context_t;
66 
67 /* DMA context. */
68 i2c_dma_context_t i2c_dma_context[QM_I2C_NUM];
69 
70 /* Define the DMA interfaces. */
71 #if (QUARK_SE)
72 qm_dma_handshake_interface_t i2c_dma_interfaces[QM_I2C_NUM][3] = {
75 #endif
76 #if (QUARK_D2000)
77 qm_dma_handshake_interface_t i2c_dma_interfaces[QM_I2C_NUM][3] = {
79 #endif
80 
81 static void i2c_dma_transmit_callback(void *callback_context, uint32_t len,
82  int error_code);
83 static void i2c_dma_receive_callback(void *callback_context, uint32_t len,
84  int error_code);
85 static int i2c_start_dma_read(const qm_i2c_t i2c);
86 void *i2c_dma_callbacks[] = {NULL, i2c_dma_transmit_callback,
87  i2c_dma_receive_callback};
88 
89 static void controller_enable(const qm_i2c_t i2c);
90 static int controller_disable(const qm_i2c_t i2c);
91 
92 /*
93  * Empty RX FIFO.
94  * Try to empty FIFO to user buffer. If RX buffer is full, trigger callback.
95  * If user does not update buffer when requested, empty FIFO without storing
96  * received data.
97  */
98 static void empty_rx_fifo(const qm_i2c_t i2c,
99  const volatile qm_i2c_transfer_t *const transfer,
100  qm_i2c_reg_t *const controller)
101 {
102  while (controller->ic_status & QM_I2C_IC_STATUS_RFNE) {
103  if (!transfer_ongoing) {
104  /* Dummy read. */
105  controller->ic_data_cmd;
106  } else {
107  if (transfer->rx_len > i2c_read_pos[i2c]) {
108  transfer->rx[i2c_read_pos[i2c]++] =
109  controller->ic_data_cmd & 0xFF;
110  }
111 
112  if (transfer->rx_len == i2c_read_pos[i2c]) {
113  /*
114  * End user transfer if user does not update
115  * buffers.
116  */
117  transfer_ongoing = false;
118 
119  if (transfer->callback) {
120  transfer->callback(
121  transfer->callback_data, 0,
122  QM_I2C_RX_FULL, transfer->rx_len);
123  }
124  }
125  }
126  }
127 }
128 
129 /*
130  * Fill TX FIFO.
131  * Try to fill the FIFO with user data. If TX buffer is empty, trigger callback.
132  * If user does not update buffer when requested, fill the FIFO with dummy
133  * data.
134  */
135 static void slave_fill_tx_fifo(const qm_i2c_t i2c,
136  const volatile qm_i2c_transfer_t *const transfer,
137  qm_i2c_reg_t *const controller)
138 {
139  while ((controller->ic_status & QM_I2C_IC_STATUS_TNF) &&
140  (!(controller->ic_intr_stat & QM_I2C_IC_INTR_STAT_TX_ABRT))) {
141  if (!transfer_ongoing) {
142  /* Dummy write. */
143  controller->ic_data_cmd = 0;
144 
145  } else {
146  if (transfer->tx_len > i2c_write_pos[i2c]) {
147  controller->ic_data_cmd =
148  transfer->tx[i2c_write_pos[i2c]++];
149  }
150 
151  if (transfer->tx_len == i2c_write_pos[i2c]) {
152  /*
153  * End user transfer if user does not update
154  * buffers.
155  */
156  transfer_ongoing = false;
157 
158  if (transfer->callback) {
159  transfer->callback(
160  transfer->callback_data, 0,
161  QM_I2C_TX_EMPTY, transfer->tx_len);
162  }
163  }
164  }
165  }
166 }
167 
168 static __inline__ int handle_tx_abrt_common(qm_i2c_reg_t *const controller,
169  qm_i2c_status_t *status)
170 {
171  int rc = 0;
172 
173  QM_ASSERT(!(controller->ic_tx_abrt_source &
174  QM_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT));
175 
176  *status = QM_I2C_TX_ABORT;
177 
178  /* Get source of TX_ABRT interrupt. */
179  *status |=
180  (controller->ic_tx_abrt_source & QM_I2C_IC_TX_ABRT_SOURCE_ALL_MASK);
181 
182  /* Clear TX ABORT interrupt. */
183  controller->ic_clr_tx_abrt;
184 
185  /* Mask interrupts. */
186  controller->ic_intr_mask = QM_I2C_IC_INTR_MASK_ALL;
187 
188  return rc = (*status & QM_I2C_TX_ABRT_USER_ABRT) ? -ECANCELED : -EIO;
189 }
190 
191 static __inline__ void
192 handle_irq_tx_abrt(const qm_i2c_t i2c,
193  const volatile qm_i2c_transfer_t *const transfer,
194  qm_i2c_reg_t *const controller)
195 {
196  qm_i2c_status_t status = 0;
197  int rc = 0;
198 
199  rc = handle_tx_abrt_common(controller, &status);
200 
201  controller_disable(i2c);
202  if (transfer->callback) {
203  transfer->callback(transfer->callback_data, rc, status,
204  i2c_write_pos[i2c]);
205  }
206 }
207 
208 static __inline__ void handle_dma_tx_abrt(const qm_i2c_t i2c,
209  qm_i2c_reg_t *const controller)
210 {
211  qm_i2c_status_t status = 0;
212  int rc = 0;
213 
214  rc = handle_tx_abrt_common(controller, &status);
215 
216  /* In DMA mode, therefore raise a flag and stop the channels. */
217  i2c_dma_context[i2c].tx_abort_status = status;
218  i2c_dma_context[i2c].i2c_error_code = rc;
219  /*
220  * When terminating the DMA transfer, the DMA controller calls
221  * the TX or RX callback, which will trigger the error callback.
222  * This will disable the I2C controller.
223  */
225 }
226 static __inline__ void
227 i2c_isr_slave_handler(const qm_i2c_t i2c,
228  const volatile qm_i2c_transfer_t *const transfer,
229  qm_i2c_reg_t *const controller)
230 {
231  /* Save register to speed up process in interrupt. */
232  uint32_t ic_intr_stat = controller->ic_intr_stat;
233 
234  /*
235  * Order of interrupt handling:
236  * - Stop interrupts
237  * - Start interrupts
238  * - RX Status interrupts
239  * - TX Status interrupts (RD_REQ, RX_DONE, TX_EMPTY)
240  * - General call (will only appear after few SCL clock cycles after
241  * start interrupt).
242  */
243 
244  /* Stop condition detected. */
245  if (ic_intr_stat & QM_I2C_IC_INTR_STAT_STOP_DETECTED) {
246  /* Empty RX FIFO. */
247  empty_rx_fifo(i2c, transfer, controller);
248 
249  /*
250  * Stop transfer if single transfer asked and controller has
251  * been addressed.
252  * Driver only knows it has been addressed if:
253  * - It already triggered an interrupt on TX_EMPTY or RX_FULL
254  * - Data was read from RX FIFO.
255  */
256  if ((transfer->stop == true) &&
257  (is_addressed || (i2c_read_pos[i2c] != 0))) {
258  controller_disable(i2c);
259  }
260 
261  if (transfer->callback) {
262  transfer->callback(
263  transfer->callback_data, 0, QM_I2C_STOP_DETECTED,
264  (transfer_ongoing) ? i2c_read_pos[i2c] : 0);
265  }
266  i2c_write_pos[i2c] = 0;
267  i2c_read_pos[i2c] = 0;
268 
269  controller->ic_intr_mask &= ~QM_I2C_IC_INTR_MASK_TX_EMPTY;
270 
271  is_addressed = false;
272 
273  /* Clear stop interrupt. */
274  controller->ic_clr_stop_det;
275 
276  /*
277  * Read again the interrupt status in case of a start interrupt
278  * has been triggered in the meantime.
279  */
280  ic_intr_stat = controller->ic_intr_stat;
281  first_start = true;
282  }
283 
284  /*
285  * START or RESTART condition detected.
286  * The RESTART_DETECTED interrupt is not used as it is redundant with
287  * the START_DETECTED interrupt.
288  */
289  if (ic_intr_stat & QM_I2C_IC_INTR_STAT_START_DETECTED) {
290  if (!first_start) {
291  empty_rx_fifo(i2c, transfer, controller);
292  }
293  if (transfer->callback) {
294  transfer->callback(
295  transfer->callback_data, 0, QM_I2C_START_DETECTED,
296  (transfer_ongoing) ? i2c_read_pos[i2c] : 0);
297  }
298  transfer_ongoing = true;
299  i2c_write_pos[i2c] = 0;
300  i2c_read_pos[i2c] = 0;
301 
302  /* Clear Start detected interrupt. */
303  controller->ic_clr_start_det;
304  first_start = false;
305  }
306 
307  /*
308  * Check RX status.
309  * Master write (TX), slave read (RX).
310  *
311  * Interrupts handled for RX status:
312  * - RX FIFO Overflow
313  * - RX FIFO Full (interrupt remains active until FIFO emptied)
314  *
315  * RX FIFO overflow must always be checked though, in case of an
316  * overflow happens during RX_FULL interrupt handling.
317  */
318  /* RX FIFO Overflow. */
319  if (ic_intr_stat & QM_I2C_IC_INTR_STAT_RX_OVER) {
320  controller->ic_clr_rx_over;
321  if (transfer->callback) {
322  transfer->callback(transfer->callback_data, 0,
323  QM_I2C_RX_OVER, 0);
324  }
325  }
326 
327  /* RX FIFO FULL. */
328  if (ic_intr_stat & QM_I2C_IC_INTR_STAT_RX_FULL) {
329  /* Empty RX FIFO. */
330  empty_rx_fifo(i2c, transfer, controller);
331 
332  /* Track activity of controller when addressed. */
333  is_addressed = true;
334  }
335 
336  /*
337  * Check TX status.
338  * Master read (RX), slave write (TX).
339  *
340  * Interrupts handled for TX status:
341  * - Read request
342  * - RX done (actually a TX state: RX done by master)
343  * - TX FIFO empty.
344  *
345  * TX FIFO empty interrupt must be handled after RX DONE interrupt: when
346  * RX DONE is triggered, TX FIFO is flushed (thus emptied) creating a
347  * TX_ABORT interrupt and a TX_EMPTY condition. TX_ABORT shall be
348  * cleared and TX_EMPTY interrupt disabled.
349  */
350  else if (ic_intr_stat & QM_I2C_IC_INTR_STAT_RD_REQ) {
351  /* Clear read request interrupt. */
352  controller->ic_clr_rd_req;
353 
354  /* Track activity of controller when addressed. */
355  is_addressed = true;
356 
357  slave_fill_tx_fifo(i2c, transfer, controller);
358 
359  /* Enable TX EMPTY interrupts. */
360  controller->ic_intr_mask |= QM_I2C_IC_INTR_MASK_TX_EMPTY;
361  } else if (ic_intr_stat & QM_I2C_IC_INTR_STAT_RX_DONE) {
362  controller->ic_clr_rx_done;
363  /* Clear TX ABORT as it is triggered when FIFO is flushed. */
364  controller->ic_clr_tx_abrt;
365 
366  /* Disable TX EMPTY interrupt. */
367  controller->ic_intr_mask &= ~QM_I2C_IC_INTR_MASK_TX_EMPTY;
368 
369  /*
370  * Read again the interrupt status in case of a stop or a start
371  * interrupt has been triggered in the meantime.
372  */
373  ic_intr_stat = controller->ic_intr_stat;
374 
375  } else if (ic_intr_stat & QM_I2C_IC_INTR_STAT_TX_EMPTY) {
376  slave_fill_tx_fifo(i2c, transfer, controller);
377  }
378 
379  /* General call detected. */
380  else if (ic_intr_stat & QM_I2C_IC_INTR_STAT_GEN_CALL_DETECTED) {
381  if (transfer->callback) {
382  transfer->callback(transfer->callback_data, 0,
384  }
385 #if (FIX_1)
386  /*
387  * Workaround.
388  * The interrupt may not actually be cleared when register is
389  * read too early.
390  */
391  while (controller->ic_intr_stat &
392  QM_I2C_IC_INTR_STAT_GEN_CALL_DETECTED) {
393  /* Clear General call interrupt. */
394  controller->ic_clr_gen_call;
395  }
396 #else
397  controller->ic_clr_gen_call;
398 #endif
399 
400  /* Track activity of controller when addressed. */
401  is_addressed = true;
402  }
403 }
404 
405 static uint32_t
406 master_fill_tx_fifo(const qm_i2c_t i2c,
407  const volatile qm_i2c_transfer_t *const transfer,
408  qm_i2c_reg_t *const controller)
409 {
410  uint32_t ic_data_cmd, count_tx = (QM_I2C_FIFO_SIZE - TX_TL);
411  uint32_t write_buffer_remaining = transfer->tx_len - i2c_write_pos[i2c];
412  uint32_t read_buffer_remaining = transfer->rx_len - i2c_read_pos[i2c];
413 
414  while ((count_tx) && write_buffer_remaining) {
415  count_tx--;
416  write_buffer_remaining--;
417 
418  /*
419  * Write command -IC_DATA_CMD[8] = 0.
420  * Fill IC_DATA_CMD[7:0] with the data.
421  */
422  ic_data_cmd = transfer->tx[i2c_write_pos[i2c]];
423 
424  /*
425  * If transfer is a combined transfer, only send stop at
426  * end of the transfer sequence.
427  */
428  if (transfer->stop && (write_buffer_remaining == 0) &&
429  (read_buffer_remaining == 0)) {
430 
431  ic_data_cmd |= QM_I2C_IC_DATA_CMD_STOP_BIT_CTRL;
432  }
433 
434  /* Write data. */
435  controller->ic_data_cmd = ic_data_cmd;
436  i2c_write_pos[i2c]++;
437 
438  /*
439  * TX_EMPTY INTR is autocleared when the buffer levels
440  * goes above the threshold.
441  */
442  }
443 
444  return write_buffer_remaining;
445 }
446 
447 static __inline__ void
448 i2c_isr_master_handler(const qm_i2c_t i2c,
449  const volatile qm_i2c_transfer_t *const transfer,
450  qm_i2c_reg_t *const controller)
451 {
452  uint32_t count_tx;
453  uint32_t read_buffer_remaining = transfer->rx_len - i2c_read_pos[i2c];
454  uint32_t write_buffer_remaining = transfer->tx_len - i2c_write_pos[i2c];
455  uint32_t missing_bytes;
456 
457  /* RX read from buffer. */
458  if (controller->ic_intr_stat & QM_I2C_IC_INTR_STAT_RX_FULL) {
459 
460  while (read_buffer_remaining && controller->ic_rxflr) {
461  transfer->rx[i2c_read_pos[i2c]] =
462  controller->ic_data_cmd;
463  read_buffer_remaining--;
464  i2c_read_pos[i2c]++;
465 
466  if (read_buffer_remaining == 0) {
467  /*
468  * Mask RX full interrupt if transfer
469  * complete.
470  */
471  controller->ic_intr_mask &=
472  ~(QM_I2C_IC_INTR_MASK_RX_FULL |
473  QM_I2C_IC_INTR_MASK_TX_EMPTY);
474 
475  if (transfer->stop) {
476  controller_disable(i2c);
477  }
478 
479  if (transfer->callback) {
480  transfer->callback(
481  transfer->callback_data, 0,
482  QM_I2C_IDLE, i2c_read_pos[i2c]);
483  }
484  }
485  }
486 
487  if (read_buffer_remaining > 0 &&
488  read_buffer_remaining < (RX_TL + 1)) {
489  /*
490  * Adjust the RX threshold so the next 'RX_FULL'
491  * interrupt is generated when all the remaining
492  * data are received.
493  */
494  controller->ic_rx_tl = read_buffer_remaining - 1;
495  }
496 
497  /*
498  * RX_FULL INTR is autocleared when the buffer levels goes below
499  * the threshold.
500  */
501  }
502 
503  if (controller->ic_intr_stat & QM_I2C_IC_INTR_STAT_TX_EMPTY) {
504 
505  if ((controller->ic_status & QM_I2C_IC_STATUS_TFE) &&
506  (transfer->tx != NULL) && (write_buffer_remaining == 0) &&
507  (read_buffer_remaining == 0)) {
508 
509  controller->ic_intr_mask &=
510  ~QM_I2C_IC_INTR_MASK_TX_EMPTY;
511 
512  /*
513  * If this is not a combined transaction, disable the
514  * controller now.
515  */
516  if (transfer->stop) {
517  controller_disable(i2c);
518  }
519 
520  /* Callback. */
521  if (transfer->callback) {
522  transfer->callback(transfer->callback_data, 0,
523  QM_I2C_IDLE,
524  i2c_write_pos[i2c]);
525  }
526  }
527 
528  write_buffer_remaining =
529  master_fill_tx_fifo(i2c, transfer, controller);
530 
531  /*
532  * If missing_bytes is not null, then that means we are already
533  * waiting for some bytes after sending read request on the
534  * previous interruption. We have to take into account this
535  * value in order to not send too much request so we won't fall
536  * into rx overflow.
537  */
538  missing_bytes = read_buffer_remaining - i2c_read_cmd_send[i2c];
539 
540  /*
541  * Sanity check: The number of read data but not processed
542  * cannot be more than the number of expected bytes.
543  */
544  QM_ASSERT(controller->ic_rxflr <= missing_bytes);
545 
546  /* Count_tx is the remaining size in the FIFO. */
547  count_tx = QM_I2C_FIFO_SIZE - controller->ic_txflr;
548 
549  if (count_tx > missing_bytes) {
550  count_tx -= missing_bytes;
551  } else {
552  count_tx = 0;
553  }
554 
555  while (i2c_read_cmd_send[i2c] &&
556  (write_buffer_remaining == 0) && count_tx) {
557  count_tx--;
558  i2c_read_cmd_send[i2c]--;
559 
560  /*
561  * If transfer is a combined transfer, only send stop at
562  * end of the transfer sequence.
563  */
564  if (transfer->stop && (i2c_read_cmd_send[i2c] == 0)) {
565  controller->ic_data_cmd =
566  QM_I2C_IC_DATA_CMD_READ |
567  QM_I2C_IC_DATA_CMD_STOP_BIT_CTRL;
568  } else {
569  controller->ic_data_cmd =
570  QM_I2C_IC_DATA_CMD_READ;
571  }
572  }
573 
574  /* Generate a tx_empty interrupt when TX FIFO is fully empty. */
575  if ((write_buffer_remaining == 0) &&
576  (read_buffer_remaining == 0)) {
577  controller->ic_tx_tl = 0;
578  }
579  }
580 }
581 
582 static void i2c_isr_irq_handler(const qm_i2c_t i2c)
583 {
584  const volatile qm_i2c_transfer_t *const transfer = i2c_transfer[i2c];
585  qm_i2c_reg_t *const controller = QM_I2C[i2c];
586 
587  /* Check TX_OVER error. */
588  if (controller->ic_intr_stat & QM_I2C_IC_INTR_STAT_TX_OVER) {
589  /* Clear interrupt. */
590  controller->ic_clr_tx_over;
591 
592  /* Mask interrupts. */
593  controller->ic_intr_mask = QM_I2C_IC_INTR_MASK_ALL;
594 
595  controller_disable(i2c);
596  if (transfer->callback) {
597  transfer->callback(transfer->callback_data, -EIO,
598  QM_I2C_TX_OVER, i2c_write_pos[i2c]);
599  }
600  }
601 
602  /* Check for RX_UNDER error. */
603  if (controller->ic_intr_stat & QM_I2C_IC_INTR_STAT_RX_UNDER) {
604  /* Clear interrupt. */
605  controller->ic_clr_rx_under;
606 
607  /* Mask interrupts. */
608  controller->ic_intr_mask = QM_I2C_IC_INTR_MASK_ALL;
609 
610  controller_disable(i2c);
611  if (transfer->callback) {
612  transfer->callback(transfer->callback_data, -EIO,
613  QM_I2C_RX_UNDER, i2c_write_pos[i2c]);
614  }
615  }
616 
617  /*
618  * TX ABORT interrupt.
619  * Avoid spurious interrupts by checking RX DONE interrupt: RX_DONE
620  * interrupt also trigger a TX_ABORT interrupt when flushing FIFO.
621  */
622  if ((controller->ic_intr_stat &
623  (QM_I2C_IC_INTR_STAT_TX_ABRT | QM_I2C_IC_INTR_STAT_RX_DONE)) ==
624  QM_I2C_IC_INTR_STAT_TX_ABRT) {
625  handle_irq_tx_abrt(i2c, transfer, controller);
626  }
627 
628  /* Master mode. */
629  if (controller->ic_con & QM_I2C_IC_CON_MASTER_MODE) {
630  /* Check for RX_OVER error. */
631  if (controller->ic_intr_stat & QM_I2C_IC_INTR_STAT_RX_OVER) {
632  /* Clear interrupt. */
633  controller->ic_clr_rx_over;
634 
635  /* Mask interrupts. */
636  controller->ic_intr_mask = QM_I2C_IC_INTR_MASK_ALL;
637 
638  controller_disable(i2c);
639  if (transfer->callback) {
640  transfer->callback(transfer->callback_data,
641  -EIO, QM_I2C_RX_OVER,
642  i2c_write_pos[i2c]);
643  }
644  }
645  i2c_isr_master_handler(i2c, transfer, controller);
646  }
647  /* Slave mode. */
648  else {
649  i2c_isr_slave_handler(i2c, transfer, controller);
650  }
651 }
652 
653 static void i2c_isr_dma_handler(const qm_i2c_t i2c)
654 {
655  const volatile qm_i2c_transfer_t *const transfer = i2c_transfer[i2c];
656  qm_i2c_reg_t *const controller = QM_I2C[i2c];
657 
658  /* Check for errors. */
659  if (controller->ic_intr_stat & QM_I2C_IC_INTR_STAT_TX_OVER) {
660  /* Clear interrupt. */
661  controller->ic_clr_tx_over;
662 
663  /* Mask interrupts. */
664  controller->ic_intr_mask = QM_I2C_IC_INTR_MASK_ALL;
665 
666  controller_disable(i2c);
667  if (transfer->callback) {
668  transfer->callback(transfer->callback_data, -EIO,
669  QM_I2C_TX_OVER, i2c_write_pos[i2c]);
670  }
671  }
672 
673  if (controller->ic_intr_stat & QM_I2C_IC_INTR_STAT_RX_UNDER) {
674  /* Clear interrupt. */
675  controller->ic_clr_rx_under;
676 
677  /* Mask interrupts. */
678  controller->ic_intr_mask = QM_I2C_IC_INTR_MASK_ALL;
679 
680  controller_disable(i2c);
681  if (transfer->callback) {
682  transfer->callback(transfer->callback_data, -EIO,
683  QM_I2C_RX_UNDER, i2c_write_pos[i2c]);
684  }
685  }
686 
687  if (controller->ic_intr_stat & QM_I2C_IC_INTR_STAT_RX_OVER) {
688  /* Clear interrupt. */
689  controller->ic_clr_rx_over;
690 
691  /* Mask interrupts. */
692  controller->ic_intr_mask = QM_I2C_IC_INTR_MASK_ALL;
693 
694  controller_disable(i2c);
695  if (transfer->callback) {
696  transfer->callback(transfer->callback_data, -EIO,
697  QM_I2C_RX_OVER, i2c_write_pos[i2c]);
698  }
699  }
700 
701  /*
702  * TX ABORT interrupt.
703  * Avoid spurious interrupts by checking RX DONE interrupt.
704  */
705 
706  if (controller->ic_intr_stat & QM_I2C_IC_INTR_STAT_TX_ABRT) {
707  handle_dma_tx_abrt(i2c, controller);
708  }
709 }
710 
711 QM_ISR_DECLARE(qm_i2c_0_irq_isr)
712 {
713  i2c_isr_irq_handler(QM_I2C_0);
714  QM_ISR_EOI(QM_IRQ_I2C_0_INT_VECTOR);
715 }
716 
717 QM_ISR_DECLARE(qm_i2c_0_dma_isr)
718 {
719  i2c_isr_dma_handler(QM_I2C_0);
720  QM_ISR_EOI(QM_IRQ_I2C_0_INT_VECTOR);
721 }
722 
723 #if (QUARK_SE)
724 QM_ISR_DECLARE(qm_i2c_1_irq_isr)
725 {
726  i2c_isr_irq_handler(QM_I2C_1);
727  QM_ISR_EOI(QM_IRQ_I2C_1_INT_VECTOR);
728 }
729 
730 QM_ISR_DECLARE(qm_i2c_1_dma_isr)
731 {
732  i2c_isr_dma_handler(QM_I2C_1);
733  QM_ISR_EOI(QM_IRQ_I2C_1_INT_VECTOR);
734 }
735 #endif
736 
737 static uint32_t get_lo_cnt(uint32_t lo_time_ns)
738 {
739  return (((get_i2c_clk_freq_in_mhz() * lo_time_ns) / 1000) - 1);
740 }
741 
742 static uint32_t get_hi_cnt(qm_i2c_t i2c, uint32_t hi_time_ns)
743 {
744  return ((((get_i2c_clk_freq_in_mhz() * hi_time_ns) / 1000) - 7 -
745  QM_I2C[i2c]->ic_fs_spklen) +
746  1);
747 }
748 
749 int qm_i2c_set_config(const qm_i2c_t i2c, const qm_i2c_config_t *const cfg)
750 {
751  uint32_t lcnt = 0, hcnt = 0, min_lcnt = 0, lcnt_diff = 0, ic_con = 0;
752  QM_CHECK(i2c < QM_I2C_NUM, -EINVAL);
753  QM_CHECK(cfg != NULL, -EINVAL);
754 
755  qm_i2c_reg_t *const controller = QM_I2C[i2c];
756 
757  i2c_dma_context[i2c].ongoing_dma_rx_operation = false;
758  i2c_dma_context[i2c].ongoing_dma_tx_operation = false;
759  /* Mask all interrupts. */
760  controller->ic_intr_mask = QM_I2C_IC_INTR_MASK_ALL;
761 
762  /* Disable controller. */
763  if (controller_disable(i2c)) {
764  return -EBUSY;
765  }
766 
767  switch (cfg->mode) {
768  case QM_I2C_MASTER:
769  /* Set mode. */
770  ic_con = QM_I2C_IC_CON_MASTER_MODE | QM_I2C_IC_CON_RESTART_EN |
771  QM_I2C_IC_CON_SLAVE_DISABLE |
772  /* Set 7/10 bit address mode. */
773  (cfg->address_mode
774  << QM_I2C_IC_CON_10BITADDR_MASTER_OFFSET);
775 
776  /*
777  * Timing generation algorithm:
778  * 1. compute hi/lo count so as to achieve the desired bus speed
779  * at 50% duty cycle
780  * 2. adjust the hi/lo count to ensure that minimum hi/lo
781  * timings are guaranteed as per spec.
782  */
783 
784  switch (cfg->speed) {
785  case QM_I2C_SPEED_STD:
786 
787  ic_con |= QM_I2C_IC_CON_SPEED_SS;
788 
789  controller->ic_fs_spklen = SPK_LEN_SS;
790 
791  min_lcnt = get_lo_cnt(QM_I2C_MIN_SS_NS);
792  lcnt = get_lo_cnt(QM_I2C_SS_50_DC_NS);
793  hcnt = get_hi_cnt(i2c, QM_I2C_SS_50_DC_NS);
794  break;
795 
796  case QM_I2C_SPEED_FAST:
797  ic_con |= QM_I2C_IC_CON_SPEED_FS_FSP;
798 
799  controller->ic_fs_spklen = SPK_LEN_FS_FSP;
800 
801  min_lcnt = get_lo_cnt(QM_I2C_MIN_FS_NS);
802  lcnt = get_lo_cnt(QM_I2C_FS_50_DC_NS);
803  hcnt = get_hi_cnt(i2c, QM_I2C_FS_50_DC_NS);
804  break;
805 
807  ic_con |= QM_I2C_IC_CON_SPEED_FS_FSP;
808 
809  controller->ic_fs_spklen = SPK_LEN_FS_FSP;
810 
811  min_lcnt = get_lo_cnt(QM_I2C_MIN_FSP_NS);
812  lcnt = get_lo_cnt(QM_I2C_FSP_50_DC_NS);
813  hcnt = get_hi_cnt(i2c, QM_I2C_FSP_50_DC_NS);
814  break;
815  }
816 
817  if (hcnt > QM_I2C_IC_HCNT_MAX || hcnt < QM_I2C_IC_HCNT_MIN) {
818  return -EINVAL;
819  }
820 
821  if (lcnt > QM_I2C_IC_LCNT_MAX || lcnt < QM_I2C_IC_LCNT_MIN) {
822  return -EINVAL;
823  }
824 
825  /* Increment minimum low count to account for rounding down. */
826  min_lcnt++;
827  if (lcnt < min_lcnt) {
828  lcnt_diff = (min_lcnt - lcnt);
829  lcnt += (lcnt_diff);
830  hcnt -= (lcnt_diff);
831  }
832  if (QM_I2C_SPEED_STD == cfg->speed) {
833  controller->ic_ss_scl_lcnt = lcnt;
834  controller->ic_ss_scl_hcnt = hcnt;
835  } else {
836  controller->ic_fs_scl_hcnt = hcnt;
837  controller->ic_fs_scl_lcnt = lcnt;
838  }
839 
840  break;
841 
842  case QM_I2C_SLAVE:
843  /*
844  * QM_I2C_IC_CON_MASTER_MODE and QM_I2C_IC_CON_SLAVE_DISABLE are
845  * deasserted.
846  */
847 
848  /* Set 7/10 bit address mode. */
849  ic_con = cfg->address_mode
850  << QM_I2C_IC_CON_10BITADDR_SLAVE_OFFSET;
851 
852  if (cfg->stop_detect_behaviour ==
854  /* Set stop interrupt only when addressed. */
855  ic_con |= QM_I2C_IC_CON_STOP_DET_IFADDRESSED;
856  }
857 
858  /* Set slave address. */
859  controller->ic_sar = cfg->slave_addr;
860  break;
861  }
862 
863  controller->ic_con = ic_con;
864  return 0;
865 }
866 
867 int qm_i2c_set_speed(const qm_i2c_t i2c, const qm_i2c_speed_t speed,
868  const uint16_t lo_cnt, const uint16_t hi_cnt)
869 {
870  QM_CHECK(i2c < QM_I2C_NUM, -EINVAL);
871  QM_CHECK(hi_cnt < QM_I2C_IC_HCNT_MAX && lo_cnt > QM_I2C_IC_HCNT_MIN,
872  -EINVAL);
873  QM_CHECK(lo_cnt < QM_I2C_IC_LCNT_MAX && lo_cnt > QM_I2C_IC_LCNT_MIN,
874  -EINVAL);
875 
876  qm_i2c_reg_t *const controller = QM_I2C[i2c];
877 
878  uint32_t ic_con = controller->ic_con;
879  ic_con &= ~QM_I2C_IC_CON_SPEED_MASK;
880 
881  switch (speed) {
882  case QM_I2C_SPEED_STD:
883  ic_con |= QM_I2C_IC_CON_SPEED_SS;
884  controller->ic_ss_scl_lcnt = lo_cnt;
885  controller->ic_ss_scl_hcnt = hi_cnt;
886  controller->ic_fs_spklen = SPK_LEN_SS;
887  break;
888 
889  case QM_I2C_SPEED_FAST:
891  ic_con |= QM_I2C_IC_CON_SPEED_FS_FSP;
892  controller->ic_fs_scl_lcnt = lo_cnt;
893  controller->ic_fs_scl_hcnt = hi_cnt;
894  controller->ic_fs_spklen = SPK_LEN_FS_FSP;
895  break;
896  }
897 
898  controller->ic_con = ic_con;
899 
900  return 0;
901 }
902 
903 int qm_i2c_get_status(const qm_i2c_t i2c, qm_i2c_status_t *const status)
904 {
905  QM_CHECK(i2c < QM_I2C_NUM, -EINVAL);
906  QM_CHECK(status != NULL, -EINVAL);
907 
908  qm_i2c_reg_t *const controller = QM_I2C[i2c];
909 
910  *status = QM_I2C_IDLE;
911 
912  /* Check if slave or master are active. */
913  if (controller->ic_status & QM_I2C_IC_STATUS_BUSY_MASK) {
914  *status = QM_I2C_BUSY;
915  }
916 
917  /* Check for abort status. */
918  *status |=
919  (controller->ic_tx_abrt_source & QM_I2C_IC_TX_ABRT_SOURCE_ALL_MASK);
920 
921  return 0;
922 }
923 
924 int qm_i2c_master_write(const qm_i2c_t i2c, const uint16_t slave_addr,
925  const uint8_t *const data, uint32_t len,
926  const bool stop, qm_i2c_status_t *const status)
927 {
928  uint8_t *d = (uint8_t *)data;
929  uint32_t ic_data_cmd = 0;
930  int rc = 0;
931 
932  QM_CHECK(i2c < QM_I2C_NUM, -EINVAL);
933  QM_CHECK(slave_addr <= QM_I2C_IC_TAR_MASK, -EINVAL);
934  QM_CHECK(data != NULL, -EINVAL);
935  QM_CHECK(len > 0, -EINVAL);
936 
937  qm_i2c_reg_t *const controller = QM_I2C[i2c];
938 
939  /* Write slave address to TAR. */
940  controller->ic_tar &= ~QM_I2C_IC_TAR_MASK;
941  controller->ic_tar |= slave_addr;
942 
943  /* Enable controller. */
944  controller_enable(i2c);
945 
946  while (len--) {
947 
948  /* Wait if FIFO is full. */
949  while (!(controller->ic_status & QM_I2C_IC_STATUS_TNF))
950  ;
951 
952  /*
953  * Write command -IC_DATA_CMD[8] = 0.
954  * Fill IC_DATA_CMD[7:0] with the data.
955  */
956  ic_data_cmd = *d;
957 
958  /* Send stop after last byte. */
959  if (len == 0 && stop) {
960  ic_data_cmd |= QM_I2C_IC_DATA_CMD_STOP_BIT_CTRL;
961  }
962 
963  controller->ic_data_cmd = ic_data_cmd;
964  d++;
965  }
966 
967  /*
968  * This is a blocking call, wait until FIFO is empty or tx abrt error.
969  */
970  while (!(controller->ic_status & QM_I2C_IC_STATUS_TFE))
971  ;
972 
973  if (controller->ic_tx_abrt_source & QM_I2C_IC_TX_ABRT_SOURCE_ALL_MASK) {
974  rc = -EIO;
975  }
976 
977  /* Disable controller. */
978  if (true == stop) {
979  if (controller_disable(i2c)) {
980  rc = -EBUSY;
981  }
982  }
983 
984  if (status != NULL) {
985  qm_i2c_get_status(i2c, status);
986  }
987 
988  /*
989  * Clear abort status.
990  * The controller flushes/resets/empties the TX FIFO whenever this bit
991  * is set. The TX FIFO remains in this flushed state until the
992  * register IC_CLR_TX_ABRT is read.
993  */
994  controller->ic_clr_tx_abrt;
995 
996  return rc;
997 }
998 
999 int qm_i2c_master_read(const qm_i2c_t i2c, const uint16_t slave_addr,
1000  uint8_t *const data, uint32_t len, const bool stop,
1001  qm_i2c_status_t *const status)
1002 {
1003  uint8_t *d = (uint8_t *)data;
1004  int rc = 0;
1005 
1006  QM_CHECK(i2c < QM_I2C_NUM, -EINVAL);
1007  QM_CHECK(slave_addr <= QM_I2C_IC_TAR_MASK, -EINVAL);
1008  QM_CHECK(data != NULL, -EINVAL);
1009  QM_CHECK(len > 0, -EINVAL);
1010 
1011  qm_i2c_reg_t *const controller = QM_I2C[i2c];
1012 
1013  /* Write slave address to TAR. */
1014  controller->ic_tar &= ~QM_I2C_IC_TAR_MASK;
1015  controller->ic_tar |= slave_addr;
1016 
1017  /* Enable controller. */
1018  controller_enable(i2c);
1019 
1020  while (len--) {
1021  if (len == 0 && stop) {
1022  controller->ic_data_cmd =
1023  QM_I2C_IC_DATA_CMD_READ |
1024  QM_I2C_IC_DATA_CMD_STOP_BIT_CTRL;
1025  }
1026 
1027  else {
1028  /* Read command -IC_DATA_CMD[8] = 1. */
1029  controller->ic_data_cmd = QM_I2C_IC_DATA_CMD_READ;
1030  }
1031 
1032  /* Wait if RX FIFO is empty, break if TX empty and error. */
1033  while (!(controller->ic_status & QM_I2C_IC_STATUS_RFNE)) {
1034 
1035  if (controller->ic_raw_intr_stat &
1036  QM_I2C_IC_RAW_INTR_STAT_TX_ABRT) {
1037  break;
1038  }
1039  }
1040 
1041  if (controller->ic_tx_abrt_source &
1042  QM_I2C_IC_TX_ABRT_SOURCE_ALL_MASK) {
1043  rc = -EIO;
1044  break;
1045  }
1046  /* IC_DATA_CMD[7:0] contains received data. */
1047  *d = controller->ic_data_cmd;
1048  d++;
1049  }
1050 
1051  /* Disable controller. */
1052  if (true == stop) {
1053  if (controller_disable(i2c)) {
1054  rc = -EBUSY;
1055  }
1056  }
1057 
1058  if (status != NULL) {
1059  qm_i2c_get_status(i2c, status);
1060  }
1061 
1062  /*
1063  * Clear abort status.
1064  * The controller flushes/resets/empties the TX FIFO whenever this bit
1065  * is set. The TX FIFO remains in this flushed state until the
1066  * register IC_CLR_TX_ABRT is read.
1067  */
1068  controller->ic_clr_tx_abrt;
1069 
1070  return rc;
1071 }
1072 
1074  const qm_i2c_transfer_t *const xfer,
1075  const uint16_t slave_addr)
1076 {
1077  QM_CHECK(i2c < QM_I2C_NUM, -EINVAL);
1078  QM_CHECK(NULL != xfer, -EINVAL);
1079  QM_CHECK(slave_addr <= QM_I2C_IC_TAR_MASK, -EINVAL);
1080 
1081  qm_i2c_reg_t *const controller = QM_I2C[i2c];
1082 
1083  /* Write slave address to TAR. */
1084  controller->ic_tar &= ~QM_I2C_IC_TAR_MASK;
1085  controller->ic_tar |= slave_addr;
1086 
1087  i2c_write_pos[i2c] = 0;
1088  i2c_read_pos[i2c] = 0;
1089  i2c_read_cmd_send[i2c] = xfer->rx_len;
1090  i2c_transfer[i2c] = xfer;
1091 
1092  /* Set threshold. */
1093  controller->ic_tx_tl = TX_TL;
1094  if (xfer->rx_len > 0 && xfer->rx_len < (RX_TL + 1)) {
1095  /*
1096  * If 'rx_len' is less than the default threshold, we have to
1097  * change the threshold value so the 'RX FULL' interrupt is
1098  * generated once all data from the transfer is received.
1099  */
1100  controller->ic_rx_tl = xfer->rx_len - 1;
1101  } else {
1102  controller->ic_rx_tl = RX_TL;
1103  }
1104 
1105  /* Mask interrupts. */
1106  QM_I2C[i2c]->ic_intr_mask = QM_I2C_IC_INTR_MASK_ALL;
1107 
1108  /* Enable controller. */
1109  controller_enable(i2c);
1110 
1111  /* Start filling tx fifo. */
1112  master_fill_tx_fifo(i2c, xfer, controller);
1113 
1114  /* Unmask interrupts. */
1115  controller->ic_intr_mask |=
1116  QM_I2C_IC_INTR_MASK_RX_UNDER | QM_I2C_IC_INTR_MASK_RX_OVER |
1117  QM_I2C_IC_INTR_MASK_RX_FULL | QM_I2C_IC_INTR_MASK_TX_OVER |
1118  QM_I2C_IC_INTR_MASK_TX_EMPTY | QM_I2C_IC_INTR_MASK_TX_ABORT;
1119 
1120  return 0;
1121 }
1122 
1124  volatile const qm_i2c_transfer_t *const xfer)
1125 {
1126  QM_CHECK(i2c < QM_I2C_NUM, -EINVAL);
1127  QM_CHECK(xfer != NULL, -EINVAL);
1128 
1129  qm_i2c_reg_t *const controller = QM_I2C[i2c];
1130 
1131  /* Assign common properties. */
1132  i2c_transfer[i2c] = xfer;
1133  i2c_write_pos[i2c] = 0;
1134  i2c_read_pos[i2c] = 0;
1135 
1136  transfer_ongoing = false;
1137  is_addressed = false;
1138  first_start = true;
1139 
1140  /* Set threshold. */
1141  controller->ic_tx_tl = TX_TL;
1142  controller->ic_rx_tl = RX_TL;
1143 
1144  controller->ic_intr_mask = QM_I2C_IC_INTR_MASK_ALL;
1145 
1146  controller_enable(i2c);
1147 
1148  /*
1149  * Almost all interrupts must be active to handle everything from the
1150  * driver, for the controller not to be stuck in a specific state.
1151  * Only TX_EMPTY must be set when needed, otherwise it will be triggered
1152  * everytime, even when it is not required to fill the TX FIFO.
1153  */
1154  controller->ic_intr_mask =
1155  QM_I2C_IC_INTR_MASK_RX_UNDER | QM_I2C_IC_INTR_MASK_RX_OVER |
1156  QM_I2C_IC_INTR_MASK_RX_FULL | QM_I2C_IC_INTR_MASK_TX_ABORT |
1157  QM_I2C_IC_INTR_MASK_RX_DONE | QM_I2C_IC_INTR_MASK_STOP_DETECTED |
1158  QM_I2C_IC_INTR_MASK_START_DETECTED | QM_I2C_IC_INTR_MASK_RD_REQ |
1159  QM_I2C_IC_INTR_MASK_GEN_CALL_DETECTED;
1160 
1161  return 0;
1162 }
1163 
1165  const qm_i2c_t i2c, volatile const qm_i2c_transfer_t *const xfer)
1166 {
1167  QM_CHECK(i2c < QM_I2C_NUM, -EINVAL);
1168  QM_CHECK(xfer != NULL, -EINVAL);
1169 
1170  /* Assign common properties. */
1171  i2c_transfer[i2c] = xfer;
1172  i2c_write_pos[i2c] = 0;
1173  i2c_read_pos[i2c] = 0;
1174 
1175  /* Tell the ISR we still have data to transfer. */
1176  transfer_ongoing = true;
1177 
1178  return 0;
1179 }
1180 
1181 static void controller_enable(const qm_i2c_t i2c)
1182 {
1183  qm_i2c_reg_t *const controller = QM_I2C[i2c];
1184 
1185  if (!(controller->ic_enable_status & QM_I2C_IC_ENABLE_STATUS_IC_EN)) {
1186  /* Enable controller. */
1187  controller->ic_enable |= QM_I2C_IC_ENABLE_CONTROLLER_EN;
1188 
1189  /* Wait until controller is enabled. */
1190  while (!(controller->ic_enable_status &
1191  QM_I2C_IC_ENABLE_STATUS_IC_EN))
1192  ;
1193  }
1194 
1195  /* Be sure that all interrupts flag are cleared. */
1196  controller->ic_clr_intr;
1197 }
1198 
1199 static int controller_disable(const qm_i2c_t i2c)
1200 {
1201  qm_i2c_reg_t *const controller = QM_I2C[i2c];
1202  int poll_count = I2C_POLL_COUNT;
1203 
1204  /* Disable controller. */
1205  controller->ic_enable &= ~QM_I2C_IC_ENABLE_CONTROLLER_EN;
1206 
1207  /* Wait until controller is disabled. */
1208  while ((controller->ic_enable_status & QM_I2C_IC_ENABLE_STATUS_IC_EN) &&
1209  poll_count--) {
1210  clk_sys_udelay(I2C_POLL_MICROSECOND);
1211  }
1212 
1213  /* Returns 0 if ok, meaning controller is disabled. */
1214  return (controller->ic_enable_status & QM_I2C_IC_ENABLE_STATUS_IC_EN);
1215 }
1216 
1218 {
1219  QM_CHECK(i2c < QM_I2C_NUM, -EINVAL);
1220 
1221  /* Abort:
1222  * In response to an ABORT, the controller issues a STOP and flushes the
1223  * Tx FIFO after completing the current transfer, then sets the TX_ABORT
1224  * interrupt after the abort operation. The ABORT bit is cleared
1225  * automatically by hardware after the abort operation.
1226  */
1227  QM_I2C[i2c]->ic_enable |= QM_I2C_IC_ENABLE_CONTROLLER_ABORT;
1228 
1229  return 0;
1230 }
1231 
1232 /*
1233  * Stops DMA channel and terminates I2C transfer.
1234  */
1236 {
1237  int rc = 0;
1238 
1239  QM_CHECK(i2c < QM_I2C_NUM, -EINVAL);
1240 
1241  if (i2c_dma_context[i2c].ongoing_dma_tx_operation) {
1242  /* First terminate the DMA transfer. */
1244  i2c_dma_context[i2c].dma_controller_id,
1245  i2c_dma_context[i2c].dma_tx_channel_id);
1246  }
1247 
1248  if (i2c_dma_context[i2c].ongoing_dma_rx_operation) {
1249  /* First terminate the DMA transfer. */
1251  i2c_dma_context[i2c].dma_controller_id,
1252  i2c_dma_context[i2c].dma_rx_channel_id);
1253  }
1254 
1255  /* Check if any of the calls failed. */
1256  if (rc != 0) {
1257  rc = -EIO;
1258  }
1259 
1260  return rc;
1261 }
1262 
1263 /*
1264  * Disable TX and/or RX and call user error callback if provided.
1265  */
1266 static void i2c_dma_transfer_error_callback(uint32_t i2c, int error_code,
1267  uint32_t len)
1268 {
1269  const volatile qm_i2c_transfer_t *const transfer = i2c_transfer[i2c];
1270 
1271  if (error_code != 0) {
1272  if (i2c_dma_context[i2c].ongoing_dma_tx_operation == true) {
1273  /* Disable DMA transmit. */
1274  QM_I2C[i2c]->ic_dma_cr &= ~QM_I2C_IC_DMA_CR_TX_ENABLE;
1275  i2c_dma_context[i2c].ongoing_dma_tx_operation = false;
1276  }
1277 
1278  if (i2c_dma_context[i2c].ongoing_dma_rx_operation == true) {
1279  /* Disable DMA receive. */
1280  QM_I2C[i2c]->ic_dma_cr &= ~QM_I2C_IC_DMA_CR_RX_ENABLE;
1281  i2c_dma_context[i2c].ongoing_dma_rx_operation = false;
1282  }
1283 
1284  /* Disable the controller. */
1285  controller_disable(i2c);
1286 
1287  /* If the user has provided a callback, let's call it. */
1288  if (transfer->callback != NULL) {
1289  transfer->callback(transfer->callback_data, error_code,
1290  i2c_dma_context[i2c].tx_abort_status,
1291  len);
1292  }
1293  }
1294 }
1295 
1296 /*
1297  * After a TX operation, a stop condition may need to be issued along the last
1298  * data byte, so that byte is handled here. DMA TX mode does also need to be
1299  * disabled.
1300  */
1301 static void i2c_dma_transmit_callback(void *callback_context, uint32_t len,
1302  int error_code)
1303 {
1304  qm_i2c_status_t status;
1305 
1306  qm_i2c_t i2c = ((i2c_dma_context_t *)callback_context)->i2c;
1307  const volatile qm_i2c_transfer_t *const transfer = i2c_transfer[i2c];
1308 
1309  if ((error_code == 0) && (i2c_dma_context[i2c].i2c_error_code == 0)) {
1310  /* Disable DMA transmit. */
1311  QM_I2C[i2c]->ic_dma_cr &= ~QM_I2C_IC_DMA_CR_TX_ENABLE;
1312  i2c_dma_context[i2c].ongoing_dma_tx_operation = false;
1313 
1314  /*
1315  * As the callback is used for both real TX and read command
1316  * "TX" during an RX operation, we need to know which case we
1317  * are in.
1318  */
1319  if (i2c_dma_context[i2c].ongoing_dma_rx_operation == false) {
1320  /* Write last byte */
1321  uint32_t data_command =
1322  QM_I2C_IC_DATA_CMD_LSB_MASK &
1323  ((uint8_t *)i2c_dma_context[i2c]
1324  .dma_tx_transfer_config.source_address)
1325  [i2c_dma_context[i2c]
1326  .dma_tx_transfer_config.block_size];
1327 
1328  /*
1329  * Check if we must issue a stop condition and it's not
1330  * a combined transaction, or bytes transfered are less
1331  * than expected.
1332  */
1333  if (((transfer->stop == true) &&
1334  (transfer->rx_len == 0)) ||
1335  (len != transfer->tx_len - 1)) {
1336  data_command |=
1337  QM_I2C_IC_DATA_CMD_STOP_BIT_CTRL;
1338  }
1339 
1340  /* Wait if FIFO is full */
1341  while (!(QM_I2C[i2c]->ic_status & QM_I2C_IC_STATUS_TNF))
1342  ;
1343  /* Write last byte and increase len count */
1344  QM_I2C[i2c]->ic_data_cmd = data_command;
1345  len++;
1346 
1347  /*
1348  * Check if there is a pending read operation, meaning
1349  * this is a combined transaction, and transfered data
1350  * length is the expected.
1351  */
1352  if ((transfer->rx_len > 0) &&
1353  (len == transfer->tx_len)) {
1354  i2c_start_dma_read(i2c);
1355  } else {
1356  /*
1357  * Let's disable the I2C controller if we are
1358  * done.
1359  */
1360  if ((transfer->stop == true) ||
1361  (len != transfer->tx_len)) {
1362  /*
1363  * This callback is called when DMA is
1364  * done, but I2C can still be
1365  * transmitting, so let's wait until all
1366  * data is sent.
1367  */
1368 
1369  while (!(QM_I2C[i2c]->ic_status &
1370  QM_I2C_IC_STATUS_TFE)) {
1371  }
1372  controller_disable(i2c);
1373  }
1374  /*
1375  * If user provided a callback, it'll be called
1376  * only if this is a TX only operation, not in a
1377  * combined transaction.
1378  */
1379  if (transfer->callback != NULL) {
1380  qm_i2c_get_status(i2c, &status);
1381  transfer->callback(
1382  transfer->callback_data, error_code,
1383  status, len);
1384  }
1385  }
1386  }
1387  } else {
1388  /*
1389  * If error code is 0, a multimaster arbitration loss has
1390  * happened, so use it as error code.
1391  */
1392  if (error_code == 0) {
1393  error_code = i2c_dma_context[i2c].i2c_error_code;
1394  }
1395 
1396  i2c_dma_transfer_error_callback(i2c, error_code, len);
1397  }
1398 }
1399 
1400 /*
1401  * After an RX operation, we need to disable DMA RX mode.
1402  */
1403 static void i2c_dma_receive_callback(void *callback_context, uint32_t len,
1404  int error_code)
1405 {
1406  qm_i2c_status_t status;
1407 
1408  qm_i2c_t i2c = ((i2c_dma_context_t *)callback_context)->i2c;
1409  const volatile qm_i2c_transfer_t *const transfer = i2c_transfer[i2c];
1410 
1411  if ((error_code == 0) && (i2c_dma_context[i2c].i2c_error_code == 0)) {
1412  /* Disable DMA receive */
1413  QM_I2C[i2c]->ic_dma_cr &= ~QM_I2C_IC_DMA_CR_RX_ENABLE;
1414  i2c_dma_context[i2c].ongoing_dma_rx_operation = false;
1415 
1416  /* Let's disable the I2C controller if we are done. */
1417  if (transfer->stop == true) {
1418  controller_disable(i2c);
1419  }
1420 
1421  /* If the user has provided a callback, let's call it. */
1422  if (transfer->callback != NULL) {
1423  qm_i2c_get_status(i2c, &status);
1424  transfer->callback(transfer->callback_data, error_code,
1425  status, len);
1426  }
1427  } else {
1428  /*
1429  * Only call the error callback on RX error.
1430  * Arbitration loss errors are handled on the TX callback.
1431  */
1432  if (error_code != 0) {
1433  i2c_dma_transfer_error_callback(i2c, error_code, len);
1434  }
1435  }
1436 }
1437 
1438 /*
1439  * Effectively starts a previously configured read operation.
1440  * For doing this, 2 DMA channels are needed, one for writting READ commands to
1441  * the I2C controller and the other to get the read data from the I2C controller
1442  * to memory. Thus, a TX operation is also needed in order to perform an RX.
1443  */
1444 static int i2c_start_dma_read(const qm_i2c_t i2c)
1445 {
1446  int rc = 0;
1447 
1448  /* Enable DMA transmit and receive. */
1449  QM_I2C[i2c]->ic_dma_cr =
1450  QM_I2C_IC_DMA_CR_RX_ENABLE | QM_I2C_IC_DMA_CR_TX_ENABLE;
1451 
1452  /* Enable controller. */
1453  controller_enable(i2c);
1454 
1455  /* A RX operation need to read and write. */
1456  i2c_dma_context[i2c].ongoing_dma_rx_operation = true;
1457  i2c_dma_context[i2c].ongoing_dma_tx_operation = true;
1458  /* Configure DMA TX for writing READ commands. */
1460  i2c_dma_context[i2c].dma_controller_id,
1461  i2c_dma_context[i2c].dma_tx_channel_id,
1462  &(i2c_dma_context[i2c].dma_cmd_transfer_config));
1463  if (rc == 0) {
1464  /* Configure DMA RX. */
1466  i2c_dma_context[i2c].dma_controller_id,
1467  i2c_dma_context[i2c].dma_rx_channel_id,
1468  &(i2c_dma_context[i2c].dma_rx_transfer_config));
1469  if (rc == 0) {
1470  /* Start both transfers "at once". */
1471  rc = qm_dma_transfer_start(
1472  i2c_dma_context[i2c].dma_controller_id,
1473  i2c_dma_context[i2c].dma_tx_channel_id);
1474  if (rc == 0) {
1475  rc = qm_dma_transfer_start(
1476  i2c_dma_context[i2c].dma_controller_id,
1477  i2c_dma_context[i2c].dma_rx_channel_id);
1478  }
1479  }
1480  }
1481 
1482  return rc;
1483 }
1484 
1485 /*
1486  * Configures given DMA channel with the appropriate width and
1487  * length and the right handshaking interface and callback depending on the
1488  * direction.
1489  */
1491  const qm_dma_t dma_controller_id,
1492  const qm_dma_channel_id_t channel_id,
1493  const qm_dma_channel_direction_t direction)
1494 {
1495  qm_dma_channel_config_t dma_channel_config = {0};
1496  int rc = 0;
1497 
1498  /* Test input values. */
1499  QM_CHECK(i2c < QM_I2C_NUM, -EINVAL);
1500  QM_CHECK(channel_id < QM_DMA_CHANNEL_NUM, -EINVAL);
1501  QM_CHECK(dma_controller_id < QM_DMA_NUM, -EINVAL);
1502  QM_CHECK(direction <= QM_DMA_PERIPHERAL_TO_MEMORY, -EINVAL);
1503  QM_CHECK(direction >= QM_DMA_MEMORY_TO_PERIPHERAL, -EINVAL);
1504 
1505  /* Set DMA channel configuration. */
1506  dma_channel_config.handshake_interface =
1507  i2c_dma_interfaces[i2c][direction];
1509  dma_channel_config.channel_direction = direction;
1510  dma_channel_config.source_transfer_width = QM_DMA_TRANS_WIDTH_8;
1511  dma_channel_config.destination_transfer_width = QM_DMA_TRANS_WIDTH_8;
1512  /* Burst length is set to half the FIFO for performance */
1513  dma_channel_config.source_burst_length = QM_DMA_BURST_TRANS_LENGTH_8;
1514  dma_channel_config.destination_burst_length =
1516  dma_channel_config.client_callback = i2c_dma_callbacks[direction];
1517  dma_channel_config.transfer_type = QM_DMA_TYPE_SINGLE;
1518 
1519  /* Hold the channel IDs and controller ID in the DMA context. */
1520  if (direction == QM_DMA_PERIPHERAL_TO_MEMORY) {
1521  i2c_dma_context[i2c].dma_rx_channel_id = channel_id;
1522  } else {
1523  i2c_dma_context[i2c].dma_tx_channel_id = channel_id;
1524  }
1525  i2c_dma_context[i2c].dma_controller_id = dma_controller_id;
1526  i2c_dma_context[i2c].i2c = i2c;
1527  dma_channel_config.callback_context = &i2c_dma_context[i2c];
1528 
1529  /* Configure DMA channel. */
1530  rc = qm_dma_channel_set_config(dma_controller_id, channel_id,
1531  &dma_channel_config);
1532 
1533  return rc;
1534 }
1535 
1536 /*
1537  * Setups and starts a DMA transaction, wether it's read, write or combined one.
1538  * In case of combined transaction, it sets up both operations and starts the
1539  * write one; the read operation will be started in the read operation
1540  * callback.
1541  */
1543  qm_i2c_transfer_t *const xfer,
1544  const uint16_t slave_addr)
1545 {
1546  int rc = 0;
1547  uint32_t i;
1548 
1549  QM_CHECK(i2c < QM_I2C_NUM, -EINVAL);
1550  QM_CHECK(NULL != xfer, -EINVAL);
1551  QM_CHECK(0 < xfer->tx_len ? xfer->tx != NULL : 1, -EINVAL);
1552  QM_CHECK(0 < xfer->rx_len ? xfer->rx != NULL : 1, -EINVAL);
1553  QM_CHECK(0 == xfer->rx_len ? xfer->tx_len != 0 : 1, -EINVAL);
1554  QM_CHECK(slave_addr <= QM_I2C_IC_TAR_MASK, -EINVAL);
1555 
1556  /* Disable all IRQs but the TX abort one. */
1557  QM_I2C[i2c]->ic_intr_mask = QM_I2C_IC_INTR_MASK_TX_ABORT;
1558 
1559  /* Write slave address to TAR. */
1560  QM_I2C[i2c]->ic_tar &= ~QM_I2C_IC_TAR_MASK;
1561  QM_I2C[i2c]->ic_tar |= slave_addr;
1562 
1563  i2c_read_cmd_send[i2c] = xfer->rx_len;
1564  i2c_transfer[i2c] = xfer;
1565 
1566  /* Set DMA TX and RX watermark levels. */
1567  QM_I2C[i2c]->ic_dma_tdlr = (QM_I2C_FIFO_SIZE / 8);
1568  /* RDLR value is desired watermark-1, according to I2C datasheet section
1569  3.17.7 */
1570  QM_I2C[i2c]->ic_dma_rdlr = (QM_I2C_FIFO_SIZE / 2) - 1;
1571 
1572  i2c_dma_context[i2c].i2c_error_code = 0;
1573 
1574  /* Setup RX if something to receive. */
1575  if (xfer->rx_len > 0) {
1576  i2c_dma_context[i2c].dma_rx_transfer_config.block_size =
1577  xfer->rx_len;
1578  i2c_dma_context[i2c].dma_rx_transfer_config.source_address =
1579  (uint32_t *)&(QM_I2C[i2c]->ic_data_cmd);
1580  i2c_dma_context[i2c]
1581  .dma_rx_transfer_config.destination_address =
1582  (uint32_t *)(xfer->rx);
1583 
1584  /*
1585  * For receiving, READ commands need to be written, a TX
1586  * transfer is needed for writting them.
1587  */
1588  i2c_dma_context[i2c].dma_cmd_transfer_config.block_size =
1589  xfer->rx_len;
1590  i2c_dma_context[i2c].dma_cmd_transfer_config.source_address =
1591  (uint32_t *)(xfer->rx);
1592  /*
1593  * RX buffer will be filled with READ commands and use it as
1594  * source for the READ command write operation. As READ commands
1595  * are written, data will be read overwriting the already
1596  * written READ commands.
1597  */
1598  for (
1599  i = 0;
1600  i < i2c_dma_context[i2c].dma_cmd_transfer_config.block_size;
1601  i++) {
1602  ((uint8_t *)xfer->rx)[i] =
1603  DATA_COMMAND_READ_COMMAND_BYTE;
1604  }
1605  /*
1606  * The STOP condition will be issued on the last READ command.
1607  */
1608  if (xfer->stop) {
1609  ((uint8_t *)xfer
1610  ->rx)[(i2c_dma_context[i2c]
1611  .dma_cmd_transfer_config.block_size -
1612  1)] |= DATA_COMMAND_STOP_BIT_BYTE;
1613  }
1614  /* Only the second byte of IC_DATA_CMD register is written. */
1615  i2c_dma_context[i2c]
1616  .dma_cmd_transfer_config.destination_address =
1617  (uint32_t *)(((uint32_t) & (QM_I2C[i2c]->ic_data_cmd)) + 1);
1618 
1619  /*
1620  * Start the RX operation in case of RX transaction only. If TX
1621  * is specified, it's a combined transaction and RX will start
1622  * once TX is done.
1623  */
1624  if (xfer->tx_len == 0) {
1625  rc = i2c_start_dma_read(i2c);
1626  }
1627  }
1628 
1629  /* Setup TX if something to transmit. */
1630  if (xfer->tx_len > 0) {
1631  /*
1632  * Last byte is handled manually as it may need to be sent with
1633  * a STOP condition.
1634  */
1635  i2c_dma_context[i2c].dma_tx_transfer_config.block_size =
1636  xfer->tx_len - 1;
1637  i2c_dma_context[i2c].dma_tx_transfer_config.source_address =
1638  (uint32_t *)xfer->tx;
1639  i2c_dma_context[i2c]
1640  .dma_tx_transfer_config.destination_address =
1641  (uint32_t *)&(QM_I2C[i2c]->ic_data_cmd);
1642 
1643  /* Enable DMA transmit. */
1644  QM_I2C[i2c]->ic_dma_cr = QM_I2C_IC_DMA_CR_TX_ENABLE;
1645 
1646  /* Enable controller. */
1647  controller_enable(i2c);
1648 
1649  /* Setup the DMA transfer. */
1651  i2c_dma_context[i2c].dma_controller_id,
1652  i2c_dma_context[i2c].dma_tx_channel_id,
1653  &(i2c_dma_context[i2c].dma_tx_transfer_config));
1654  if (rc == 0) {
1655  /* Mark the TX operation as ongoing. */
1656  i2c_dma_context[i2c].ongoing_dma_rx_operation = false;
1657  i2c_dma_context[i2c].ongoing_dma_tx_operation = true;
1658  rc = qm_dma_transfer_start(
1659  i2c_dma_context[i2c].dma_controller_id,
1660  i2c_dma_context[i2c].dma_tx_channel_id);
1661  }
1662  }
1663 
1664  return rc;
1665 }
1666 
1667 #if (ENABLE_RESTORE_CONTEXT)
1669 {
1670  QM_CHECK(i2c < QM_I2C_NUM, -EINVAL);
1671  QM_CHECK(ctx != NULL, -EINVAL);
1672 
1673  qm_i2c_reg_t *const regs = QM_I2C[i2c];
1674 
1675  ctx->con = regs->ic_con;
1676  ctx->sar = regs->ic_sar;
1677  ctx->ss_scl_hcnt = regs->ic_ss_scl_hcnt;
1678  ctx->ss_scl_lcnt = regs->ic_ss_scl_lcnt;
1679  ctx->fs_scl_hcnt = regs->ic_fs_scl_hcnt;
1680  ctx->fs_scl_lcnt = regs->ic_fs_scl_lcnt;
1681  ctx->fs_spklen = regs->ic_fs_spklen;
1682  ctx->ic_intr_mask = regs->ic_intr_mask;
1683  ctx->enable = regs->ic_enable;
1684  ctx->rx_tl = regs->ic_rx_tl;
1685  ctx->tx_tl = regs->ic_tx_tl;
1686 
1687  return 0;
1688 }
1689 
1691  const qm_i2c_context_t *const ctx)
1692 {
1693  QM_CHECK(i2c < QM_I2C_NUM, -EINVAL);
1694  QM_CHECK(ctx != NULL, -EINVAL);
1695 
1696  qm_i2c_reg_t *const regs = QM_I2C[i2c];
1697 
1698  regs->ic_con = ctx->con;
1699  regs->ic_sar = ctx->sar;
1700  regs->ic_ss_scl_hcnt = ctx->ss_scl_hcnt;
1701  regs->ic_ss_scl_lcnt = ctx->ss_scl_lcnt;
1702  regs->ic_fs_scl_hcnt = ctx->fs_scl_hcnt;
1703  regs->ic_fs_scl_lcnt = ctx->fs_scl_lcnt;
1704  regs->ic_fs_spklen = ctx->fs_spklen;
1705  regs->ic_intr_mask = ctx->ic_intr_mask;
1706  regs->ic_enable = ctx->enable;
1707  regs->ic_rx_tl = ctx->rx_tl;
1708  regs->ic_tx_tl = ctx->tx_tl;
1709 
1710  return 0;
1711 }
1712 #else
1713 int qm_i2c_save_context(const qm_i2c_t i2c, qm_i2c_context_t *const ctx)
1714 {
1715  (void)i2c;
1716  (void)ctx;
1717 
1718  return 0;
1719 }
1720 
1721 int qm_i2c_restore_context(const qm_i2c_t i2c,
1722  const qm_i2c_context_t *const ctx)
1723 {
1724  (void)i2c;
1725  (void)ctx;
1726 
1727  return 0;
1728 }
1729 #endif /* ENABLE_RESTORE_CONTEXT */
Slave mode.
Definition: qm_i2c.h:46
int qm_i2c_master_dma_transfer(const qm_i2c_t i2c, qm_i2c_transfer_t *const xfer, const uint16_t slave_addr)
Perform a DMA based master transfer on the I2C bus.
Definition: qm_i2c.c:1542
QM_RW uint32_t ic_fs_spklen
SS and FS Spike Suppression Limit.
Definition: qm_soc_regs.h:911
QM_RW uint32_t ic_status
Status.
Definition: qm_soc_regs.h:899
Controller busy.
Definition: qm_i2c.h:85
int qm_i2c_save_context(const qm_i2c_t i2c, qm_i2c_context_t *const ctx)
Save I2C context.
Definition: qm_i2c.c:1668
uint32_t tx_len
Write data length.
Definition: qm_i2c.h:132
qm_i2c_speed_t speed
Standard, fast or fast plus mode.
Definition: qm_i2c.h:112
DMA channel configuration structure.
Definition: qm_dma.h:77
int qm_i2c_master_write(const qm_i2c_t i2c, const uint16_t slave_addr, const uint8_t *const data, uint32_t len, const bool stop, qm_i2c_status_t *const status)
Master write on I2C.
Definition: qm_i2c.c:924
qm_dma_transfer_type_t transfer_type
DMA transfer type.
Definition: qm_dma.h:100
QM_RW uint32_t ic_intr_stat
Interrupt Status.
Definition: qm_soc_regs.h:881
int qm_i2c_master_read(const qm_i2c_t i2c, const uint16_t slave_addr, uint8_t *const data, uint32_t len, const bool stop, qm_i2c_status_t *const status)
Master read of I2C.
Definition: qm_i2c.c:999
I2C register map.
Definition: qm_soc_regs.h:864
int qm_i2c_set_config(const qm_i2c_t i2c, const qm_i2c_config_t *const cfg)
Set I2C configuration.
Definition: qm_i2c.c:749
int qm_i2c_set_speed(const qm_i2c_t i2c, const qm_i2c_speed_t speed, const uint16_t lo_cnt, const uint16_t hi_cnt)
Set I2C speed.
Definition: qm_i2c.c:867
QM_RW uint32_t ic_clr_intr
Clear Combined and Individual Interrupt.
Definition: qm_soc_regs.h:887
Burst length 8 data items.
Definition: qm_dma.h:32
QM_RW uint32_t ic_clr_rx_under
Clear RX_UNDER Interrupt.
Definition: qm_soc_regs.h:888
qm_dma_t
DMA instances.
Definition: qm_soc_regs.h:1480
QM_RW uint32_t ic_clr_rx_over
Clear RX_OVER Interrupt.
Definition: qm_soc_regs.h:889
uint32_t tx_tl
Receive FIFO threshold register.
Definition: qm_soc_regs.h:1271
Rx underflow.
Definition: qm_i2c.h:89
uint32_t fs_scl_hcnt
Fast Speed Clock SCL High Count.
Definition: qm_soc_regs.h:1265
void * callback_data
User callback data.
Definition: qm_i2c.h:163
uint8_t * tx
Write data.
Definition: qm_i2c.h:131
QM_RW uint32_t ic_ss_scl_lcnt
Standard Speed Clock SCL Low Count.
Definition: qm_soc_regs.h:873
uint32_t get_i2c_clk_freq_in_mhz(void)
Get I2C clock frequency in MHz.
Definition: clk.c:381
uint32_t con
Control Register.
Definition: qm_soc_regs.h:1261
QM_RW uint32_t ic_enable
Enable.
Definition: qm_soc_regs.h:898
Number of DMA channels.
Definition: qm_soc_regs.h:1489
DMA single block transfer configuration structure.
Definition: qm_dma.h:133
QM_RW uint32_t ic_clr_rx_done
Clear RX_DONE Interrupt.
Definition: qm_soc_regs.h:893
qm_dma_burst_length_t source_burst_length
DMA source burst length.
Definition: qm_dma.h:94
QM_RW uint32_t ic_tx_tl
Transmit FIFO Threshold Level.
Definition: qm_soc_regs.h:885
qm_i2c_slave_stop_t stop_detect_behaviour
Slave stop detect behaviour.
Definition: qm_i2c.h:118
QM_RW uint32_t ic_fs_scl_lcnt
Fast Speed I2C Clock SCL Low Count.
Definition: qm_soc_regs.h:876
Rx overflow.
Definition: qm_i2c.h:88
QM_RW uint32_t ic_clr_tx_abrt
Clear TX_ABRT Interrupt.
Definition: qm_soc_regs.h:892
QM_RW uint32_t ic_data_cmd
Data Buffer and Command.
Definition: qm_soc_regs.h:869
QM_RW uint32_t ic_clr_stop_det
Clear STOP_DET Interrupt.
Definition: qm_soc_regs.h:895
void * callback_context
DMA client context passed to the callbacks.
Definition: qm_dma.h:113
int qm_i2c_dma_channel_config(const qm_i2c_t i2c, const qm_dma_t dma_controller_id, const qm_dma_channel_id_t channel_id, const qm_dma_channel_direction_t direction)
Configure a DMA channel with a specific transfer direction.
Definition: qm_i2c.c:1490
bool stop
Master: Generate STOP.
Definition: qm_i2c.h:140
Transfer width of 8 bits.
Definition: qm_dma.h:45
uint32_t fs_scl_lcnt
Fast Speed I2C Clock SCL Low Count.
Definition: qm_soc_regs.h:1266
int qm_i2c_irq_transfer_terminate(const qm_i2c_t i2c)
Terminate I2C IRQ transfer.
Definition: qm_i2c.c:1217
Fast mode (400 Kbps).
Definition: qm_i2c.h:54
uint16_t slave_addr
I2C address when in slave mode.
Definition: qm_i2c.h:115
QM_RW uint32_t ic_rxflr
Receive FIFO Level.
Definition: qm_soc_regs.h:901
QM_RW uint32_t ic_clr_tx_over
Clear TX_OVER Interrupt.
Definition: qm_soc_regs.h:890
QM_RW uint32_t ic_raw_intr_stat
Raw Interrupt Status.
Definition: qm_soc_regs.h:883
qm_dma_handshake_interface_t handshake_interface
DMA channel handshake interface ID.
Definition: qm_dma.h:79
qm_i2c_status_t
I2C status type.
Definition: qm_i2c.h:61
User abort.
Definition: qm_i2c.h:84
int qm_dma_transfer_set_config(const qm_dma_t dma, const qm_dma_channel_id_t channel_id, qm_dma_transfer_t *const transfer_config)
Setup a DMA single block transfer.
Definition: qm_dma.c:345
int qm_i2c_master_irq_transfer(const qm_i2c_t i2c, const qm_i2c_transfer_t *const xfer, const uint16_t slave_addr)
Interrupt based master transfer on I2C.
Definition: qm_i2c.c:1073
TX buffer empty.
Definition: qm_i2c.h:91
qm_i2c_speed_t
QM I2C speed type.
Definition: qm_i2c.h:52
int qm_i2c_get_status(const qm_i2c_t i2c, qm_i2c_status_t *const status)
Retrieve I2C bus status.
Definition: qm_i2c.c:903
int qm_i2c_slave_irq_transfer(const qm_i2c_t i2c, volatile const qm_i2c_transfer_t *const xfer)
Interrupt based slave transfer on I2C.
Definition: qm_i2c.c:1123
qm_dma_handshake_polarity_t handshake_polarity
DMA channel handshake polarity.
Definition: qm_dma.h:82
Start or restart detected.
Definition: qm_i2c.h:90
Single block mode.
Definition: qm_dma.h:67
QM_RW uint32_t ic_fs_scl_hcnt
Fast Speed Clock SCL High Count.
Definition: qm_soc_regs.h:874
qm_i2c_mode_t mode
Master or slave mode.
Definition: qm_i2c.h:114
QM_RW uint32_t ic_clr_start_det
Clear START_DET Interrupt.
Definition: qm_soc_regs.h:896
Peripheral to memory transfer.
Definition: qm_dma.h:60
qm_dma_burst_length_t destination_burst_length
DMA destination burst length.
Definition: qm_dma.h:97
void clk_sys_udelay(uint32_t microseconds)
Idle loop the processor for at least the value given in microseconds.
Definition: clk.c:352
qm_dma_transfer_width_t destination_transfer_width
DMA destination transfer width.
Definition: qm_dma.h:91
int qm_dma_channel_set_config(const qm_dma_t dma, const qm_dma_channel_id_t channel_id, qm_dma_channel_config_t *const channel_config)
Setup a DMA channel configuration.
Definition: qm_dma.c:254
QM_RW uint32_t ic_ss_scl_hcnt
Standard Speed Clock SCL High Count.
Definition: qm_soc_regs.h:871
Burst length 4 data items.
Definition: qm_dma.h:31
int qm_i2c_slave_irq_transfer_update(const qm_i2c_t i2c, volatile const qm_i2c_transfer_t *const xfer)
I2C interrupt based slave transfer buffer update.
Definition: qm_i2c.c:1164
uint32_t ss_scl_lcnt
Standard Speed Clock SCL Low Count.
Definition: qm_soc_regs.h:1264
uint32_t ss_scl_hcnt
Standard Speed Clock SCL High Count.
Definition: qm_soc_regs.h:1263
I2C_Master_0_RX.
Definition: qm_soc_regs.h:1503
QM_RW uint32_t ic_sar
Slave Address.
Definition: qm_soc_regs.h:867
Number of DMA controllers.
Definition: qm_soc_regs.h:1482
I2C_Master_0_TX.
Definition: qm_soc_regs.h:1502
qm_dma_transfer_width_t source_transfer_width
DMA source transfer width.
Definition: qm_dma.h:88
int qm_dma_transfer_terminate(const qm_dma_t dma, const qm_dma_channel_id_t channel_id)
Terminate a DMA transfer.
Definition: qm_dma.c:618
qm_dma_channel_direction_t
DMA channel direction.
Definition: qm_dma.h:56
uint32_t ic_intr_mask
I2C Interrupt Mask.
Definition: qm_soc_regs.h:1269
QM_RW uint32_t ic_clr_gen_call
Clear GEN_CALL Interrupt.
Definition: qm_soc_regs.h:897
void(* callback)(void *data, int rc, qm_i2c_status_t status, uint32_t len)
Transfer callback.
Definition: qm_i2c.h:161
int qm_dma_transfer_start(const qm_dma_t dma, const qm_dma_channel_id_t channel_id)
Start a DMA transfer.
Definition: qm_dma.c:582
uint8_t * rx
Read data.
Definition: qm_i2c.h:133
uint32_t enable
Enable.
Definition: qm_soc_regs.h:1267
Set HS polarity high.
Definition: qm_dma.h:22
uint32_t rx_len
Read buffer length.
Definition: qm_i2c.h:134
Trigger interrupt only if this slave is being addressed.
Definition: qm_i2c.h:105
Tx overflow.
Definition: qm_i2c.h:87
QM_RW uint32_t ic_intr_mask
Interrupt Mask.
Definition: qm_soc_regs.h:882
qm_i2c_t
Number of I2C controllers.
Definition: qm_soc_regs.h:861
I2C_Master_1_RX.
Definition: qm_soc_regs.h:1750
Stop detected.
Definition: qm_i2c.h:94
Memory to peripheral transfer.
Definition: qm_dma.h:58
qm_i2c_reg_t * qm_i2c[QM_I2C_NUM]
I2C register block.
Definition: qm_i2c.c:20
QM_RW uint32_t ic_tx_abrt_source
Transmit Abort Source.
Definition: qm_soc_regs.h:903
I2C transfer type.
Definition: qm_i2c.h:130
Controller idle.
Definition: qm_i2c.h:62
Fast plus mode (1 Mbps).
Definition: qm_i2c.h:55
I2C context to be saved between sleep/resume.
Definition: qm_soc_regs.h:1260
Standard mode (100 Kbps).
Definition: qm_i2c.h:53
QM_ISR_DECLARE(qm_i2c_0_irq_isr)
ISR for I2C 0 irq mode transfer interrupt.
Definition: qm_i2c.c:711
I2C_Master_1_TX.
Definition: qm_soc_regs.h:1749
int qm_i2c_dma_transfer_terminate(const qm_i2c_t i2c)
Terminate any DMA transfer going on on the controller.
Definition: qm_i2c.c:1235
Master mode.
Definition: qm_i2c.h:45
uint32_t fs_spklen
SS and FS Spike Suppression Limit.
Definition: qm_soc_regs.h:1268
I2C configuration type.
Definition: qm_i2c.h:111
qm_dma_channel_id_t
DMA channel IDs.
Definition: qm_soc_regs.h:1486
qm_dma_handshake_interface_t
DMA hardware handshake interfaces.
Definition: qm_soc_regs.h:1493
Tx abort.
Definition: qm_i2c.h:86
QM_RW uint32_t ic_enable_status
Enable Status.
Definition: qm_soc_regs.h:910
int qm_i2c_restore_context(const qm_i2c_t i2c, const qm_i2c_context_t *const ctx)
Restore I2C context.
Definition: qm_i2c.c:1690
QM_RW uint32_t ic_con
Control Register.
Definition: qm_soc_regs.h:865
QM_RW uint32_t ic_tar
Master Target Address.
Definition: qm_soc_regs.h:866
qm_dma_channel_direction_t channel_direction
DMA channel direction.
Definition: qm_dma.h:85
uint32_t sar
Slave Address.
Definition: qm_soc_regs.h:1262
RX buffer full.
Definition: qm_i2c.h:92
QM_RW uint32_t ic_rx_tl
Receive FIFO Threshold Level.
Definition: qm_soc_regs.h:884
QM_RW uint32_t ic_txflr
Transmit FIFO Level.
Definition: qm_soc_regs.h:900
qm_i2c_addr_t address_mode
7 bit or 10 bit addressing.
Definition: qm_i2c.h:113
QM_RW uint32_t ic_clr_rd_req
Clear RD_REQ Interrupt.
Definition: qm_soc_regs.h:891
void(* client_callback)(void *callback_context, uint32_t len, int error_code)
Client callback for DMA transfer ISR.
Definition: qm_dma.h:109