Intel® Quark™ Microcontroller Software Interface  1.4.0
Intel® Quark™ Microcontroller BSP
qm_spi.h
1 /*
2  * {% copyright %}
3  */
4 
5 #ifndef __QM_SPI_H__
6 #define __QM_SPI_H__
7 
8 #include "qm_common.h"
9 #include "qm_soc_regs.h"
10 #include "qm_dma.h"
11 
12 /**
13  * SPI peripheral driver for Quark Microcontrollers.
14  *
15  * @defgroup groupSPI SPI
16  * @{
17  */
18 
19 /**
20  * QM SPI frame size type.
21  */
22 typedef enum {
23  QM_SPI_FRAME_SIZE_4_BIT = 3, /**< 4 bit frame. */
24  QM_SPI_FRAME_SIZE_5_BIT, /**< 5 bit frame. */
25  QM_SPI_FRAME_SIZE_6_BIT, /**< 6 bit frame. */
26  QM_SPI_FRAME_SIZE_7_BIT, /**< 7 bit frame. */
27  QM_SPI_FRAME_SIZE_8_BIT, /**< 8 bit frame. */
28  QM_SPI_FRAME_SIZE_9_BIT, /**< 9 bit frame. */
29  QM_SPI_FRAME_SIZE_10_BIT, /**< 10 bit frame. */
30  QM_SPI_FRAME_SIZE_11_BIT, /**< 11 bit frame. */
31  QM_SPI_FRAME_SIZE_12_BIT, /**< 12 bit frame. */
32  QM_SPI_FRAME_SIZE_13_BIT, /**< 13 bit frame. */
33  QM_SPI_FRAME_SIZE_14_BIT, /**< 14 bit frame. */
34  QM_SPI_FRAME_SIZE_15_BIT, /**< 15 bit frame. */
35  QM_SPI_FRAME_SIZE_16_BIT, /**< 16 bit frame. */
36  QM_SPI_FRAME_SIZE_17_BIT, /**< 17 bit frame. */
37  QM_SPI_FRAME_SIZE_18_BIT, /**< 18 bit frame. */
38  QM_SPI_FRAME_SIZE_19_BIT, /**< 19 bit frame. */
39  QM_SPI_FRAME_SIZE_20_BIT, /**< 20 bit frame. */
40  QM_SPI_FRAME_SIZE_21_BIT, /**< 21 bit frame. */
41  QM_SPI_FRAME_SIZE_22_BIT, /**< 22 bit frame. */
42  QM_SPI_FRAME_SIZE_23_BIT, /**< 23 bit frame. */
43  QM_SPI_FRAME_SIZE_24_BIT, /**< 24 bit frame. */
44  QM_SPI_FRAME_SIZE_25_BIT, /**< 25 bit frame. */
45  QM_SPI_FRAME_SIZE_26_BIT, /**< 26 bit frame. */
46  QM_SPI_FRAME_SIZE_27_BIT, /**< 27 bit frame. */
47  QM_SPI_FRAME_SIZE_28_BIT, /**< 28 bit frame. */
48  QM_SPI_FRAME_SIZE_29_BIT, /**< 29 bit frame. */
49  QM_SPI_FRAME_SIZE_30_BIT, /**< 30 bit frame. */
50  QM_SPI_FRAME_SIZE_31_BIT, /**< 31 bit frame. */
51  QM_SPI_FRAME_SIZE_32_BIT /**< 32 bit frame. */
53 
54 /**
55  * SPI transfer mode type.
56  */
57 typedef enum {
58  QM_SPI_TMOD_TX_RX, /**< Transmit & Receive. */
59  QM_SPI_TMOD_TX, /**< Transmit Only. */
60  QM_SPI_TMOD_RX, /**< Receive Only. */
61  QM_SPI_TMOD_EEPROM_READ /**< EEPROM Read. */
63 
64 /**
65  * SPI bus mode type.
66  */
67 typedef enum {
68  QM_SPI_BMODE_0, /**< Clock Polarity = 0, Clock Phase = 0. */
69  QM_SPI_BMODE_1, /**< Clock Polarity = 0, Clock Phase = 1. */
70  QM_SPI_BMODE_2, /**< Clock Polarity = 1, Clock Phase = 0. */
71  QM_SPI_BMODE_3 /**< Clock Polarity = 1, Clock Phase = 1. */
73 
74 /**
75  * SPI slave select type.
76  *
77  * Slave selects can combined by logical OR if multiple slaves are selected
78  * during one transfer. Setting only QM_SPI_SS_DISABLED prevents the controller
79  * from starting the transfer.
80  */
81 typedef enum {
82  QM_SPI_SS_DISABLED = 0, /**< Slave select disable. */
83  QM_SPI_SS_0 = BIT(0), /**< Slave Select 0. */
84  QM_SPI_SS_1 = BIT(1), /**< Slave Select 1. */
85  QM_SPI_SS_2 = BIT(2), /**< Slave Select 2. */
86  QM_SPI_SS_3 = BIT(3), /**< Slave Select 3. */
88 
89 /**
90  * SPI status
91  */
92 typedef enum {
93  QM_SPI_IDLE, /**< SPI device is not in use. */
94  QM_SPI_BUSY, /**< SPI device is busy. */
95  QM_SPI_RX_OVERFLOW, /**< RX transfer has overflown. */
96  QM_SPI_RX_FULL, /**< Appl. Rx buffer full (slave only). */
97  QM_SPI_TX_EMPTY /**< Appl. Tx buffer empty (slave only) . */
99 
100 /**
101  * QM SPI Frame Format
102  */
103 typedef enum {
104  /**< Standard SPI mode */
107 
108 /*
109  * SPI update type
110  *
111  * Used by qm_spi_irq_update to know what to update, RX or TX.
112  * Logical OR can be used in order to update both RX and TX.
113  */
114 typedef enum {
115  QM_SPI_UPDATE_RX = BIT(0), /* Update RX. */
116  QM_SPI_UPDATE_TX = BIT(1), /* Update TX. */
117 } qm_spi_update_t;
118 
119 /*
120  * SPI configuration type.
121  */
122 typedef struct {
123  qm_spi_frame_size_t frame_size; /**< Frame Size. */
124  qm_spi_tmode_t transfer_mode; /**< Transfer mode (enum). */
125  qm_spi_bmode_t bus_mode; /**< Bus mode (enum). */
126  qm_spi_frame_format_t frame_format; /* Data frame format for TX/RX */
127 
128  /**
129  * SCK = SPI_clock/clk_divider.
130  *
131  * A value of 0 will disable SCK.
132  */
133  uint16_t clk_divider;
134 } qm_spi_config_t;
135 
136 /**
137  * SPI aynchronous transfer type.
138  *
139  * If the frame size is 8 bits or less, 1 byte is needed per data frame. If the
140  * frame size is 9-16 bits, 2 bytes are needed per data frame and frames of more
141  * than 16 bits require 4 bytes. In each case, the least significant bits are
142  * sent while the extra bits are discarded. The most significant bits of the
143  * frame are sent first.
144  */
145 typedef struct {
146  void *tx; /**< Write data. */
147  void *rx; /**< Read data. */
148  uint16_t tx_len; /**< Number of data frames to write. */
149  uint16_t rx_len; /**< Number of data frames to read. */
150  bool keep_enabled; /**< Keep device on once transfer is done. */
151 
152  /**
153  * Transfer callback.
154  *
155  * Called after all data is transmitted/received or if the driver
156  * detects an error during the SPI transfer.
157  * For slave device it also allows the application to update
158  * transfer information by calling the qm_spi_irq_update function.
159  *
160  * @param[in] data The callback user data.
161  * @param[in] error 0 on success.
162  * Negative @ref errno for possible error codes.
163  * @param[in] status SPI driver status.
164  * @param[in] len Length of the SPI transfer if successful, 0
165  * otherwise.
166  */
167  void (*callback)(void *data, int error, qm_spi_status_t status,
168  uint16_t len);
169  void *callback_data; /**< Callback user data. */
171 
172 /**
173  * SPI synchronous transfer type.
174  *
175  * If the frame size is 8 bits or less, 1 byte is needed per data frame. If the
176  * frame size is 9-16 bits, 2 bytes are needed per data frame and frames of more
177  * than 16 bits require 4 bytes. In each case, the least significant bits are
178  * sent while the extra bits are discarded. The most significant bits of the
179  * frame are sent first.
180  */
181 typedef struct {
182  void *tx; /**< Write data. */
183  void *rx; /**< Read data. */
184  uint16_t tx_len; /**< Number of data frames to write. */
185  uint16_t rx_len; /**< Number of data frames to read. */
187 
188 /**
189  * Set SPI configuration.
190  *
191  * Change the configuration of a SPI module.
192  * This includes transfer mode, bus mode, clock divider and data frame size.
193  *
194  * @param[in] spi Which SPI module to configure.
195  * @param[in] cfg New configuration for SPI. This must not be NULL.
196  *
197  * @return Standard errno return type for QMSI.
198  * @retval 0 on success.
199  * @retval Negative @ref errno for possible error codes.
200  */
201 int qm_spi_set_config(const qm_spi_t spi, const qm_spi_config_t *const cfg);
202 
203 /**
204  * Select which slave to perform SPI transmissions on.
205  *
206  * @param[in] spi Which SPI module to configure.
207  * @param[in] ss Which slave select line to enable when doing transmissions.
208  *
209  * @return Standard errno return type for QMSI.
210  * @retval 0 on success.
211  * @retval Negative @ref errno for possible error codes.
212  */
213 int qm_spi_slave_select(const qm_spi_t spi, const qm_spi_slave_select_t ss);
214 
215 /**
216  * Get SPI bus status.
217  *
218  * Retrieve SPI bus status. Return QM_SPI_BUSY if transmitting data or SPI TX
219  * FIFO not empty; QM_SPI_IDLE is available for transfer; QM_SPI_RX_OVERFLOW if
220  * an RX overflow has occurred.
221  *
222  * The user may call this function before performing an SPI transfer in order to
223  * guarantee that the SPI interface is available.
224  *
225  * @param[in] spi Which SPI to read the status of.
226  * @param[out] status Current SPI status. This must not be null.
227  *
228  * @return Standard errno return type for QMSI.
229  * @retval 0 on success.
230  * @retval Negative @ref errno for possible error codes.
231  */
232 int qm_spi_get_status(const qm_spi_t spi, qm_spi_status_t *const status);
233 
234 /**
235  * Multi-frame read / write on SPI.
236  *
237  * Perform a multi-frame read/write on the SPI bus. This is a blocking
238  * synchronous call. If the SPI is currently in use, the function will wait
239  * until the SPI is free before beginning the transfer. If transfer mode is
240  * full duplex (QM_SPI_TMOD_TX_RX), then tx_len and rx_len must be equal.
241  * Similarly, for transmit-only transfers (QM_SPI_TMOD_TX) rx_len must be 0,
242  * while for receive-only transfers (QM_SPI_TMOD_RX) tx_len must be 0.
243  *
244  * For starting a transfer, this controller demands at least one slave
245  * select line (SS) to be enabled. Thus, a call to qm_spi_slave_select()
246  * with one of the four SS valid lines is mandatory. This is true even if
247  * the native slave select line is not used (i.e. when a GPIO is used to
248  * drive the SS signal manually).
249  *
250  * @param[in] spi Which SPI to read/write on.
251  * @param[in] xfer Structure containing pre-allocated write and read data
252  * buffers. This must not be NULL.
253  * @param[out] status Get spi status.
254  *
255  * @return Standard errno return type for QMSI.
256  * @retval 0 on success.
257  * @retval Negative @ref errno for possible error codes.
258  */
259 int qm_spi_transfer(const qm_spi_t spi, const qm_spi_transfer_t *const xfer,
260  qm_spi_status_t *const status);
261 
262 /**
263  * Interrupt based transfer on SPI.
264  *
265  * Perform an interrupt based transfer on the SPI bus. The function will
266  * replenish/empty TX/RX FIFOs on SPI empty/full interrupts. If transfer
267  * mode is full duplex (QM_SPI_TMOD_TX_RX), then tx_len and rx_len must be
268  * equal. For transmit-only transfers (QM_SPI_TMOD_TX) rx_len must be 0
269  * while for receive-only transfers (QM_SPI_TMOD_RX) tx_len must be 0.
270  *
271  * For starting a transfer, this controller demands at least one slave
272  * select line (SS) to be enabled. Thus, a call to qm_spi_slave_select()
273  * with one of the four SS valid lines is mandatory. This is true even if
274  * the native slave select line is not used (i.e. when a GPIO is used to
275  * drive the SS signal manually).
276  *
277  * @param[in] spi Which SPI to transfer to / from.
278  * @param[in] xfer Transfer structure includes write / read buffers, length,
279  * user callback function and the callback context data.
280  * The structure must not be NULL and must be kept valid until
281  * the transfer is complete.
282  *
283  * @return Standard errno return type for QMSI.
284  * @retval 0 on success.
285  * @retval Negative @ref errno for possible error codes.
286  */
287 int qm_spi_irq_transfer(const qm_spi_t spi,
288  volatile const qm_spi_async_transfer_t *const xfer);
289 
290 /**
291  * Update parameters of Interrupt based transfer on SPI.
292  *
293  * Allow the application to transmit and/or receive more data over the current
294  * SPI communication.
295  * The application is supposed to call this function only inside the registered
296  * callback, once notified from the driver.
297  * It is strongly recommended to use this function for slave-based applications
298  * only, as slave controllers usually do not know how many frames an external
299  * master will send or request before starting the communication.
300  * Master controllers should not use this function as it will most likely
301  * corrupt the transaction.
302  *
303  * @param[in] spi Which SPI to transfer to / from.
304  * @param[in] xfer Transfer structure includes write / read buffers, length,
305  * user callback function and the callback context data.
306  * The structure must not be NULL and must be kept valid until
307  * the transfer is complete.
308  * @param[in] update Specify if only RX has to be updated, or only TX or both.
309  *
310  * @return Standard errno return type for QMSI.
311  * @retval 0 on success.
312  * @retval Negative @ref errno for possible error codes.
313  */
314 int qm_spi_irq_update(const qm_spi_t spi,
315  volatile const qm_spi_async_transfer_t *const xfer,
316  const qm_spi_update_t update);
317 
318 /**
319  * Configure a DMA channel with a specific transfer direction.
320  *
321  * The user is responsible for managing the allocation of the pool of DMA
322  * channels provided by each DMA core to the different peripheral drivers
323  * that require them.
324  *
325  * Note that a SPI controller cannot use different DMA cores to manage
326  * transfers in different directions.
327  *
328  * This function configures DMA channel parameters that are unlikely to change
329  * between transfers, like transaction width, burst size, and handshake
330  * interface parameters. The user will likely only call this function once for
331  * the lifetime of an application unless the channel needs to be repurposed.
332  *
333  * This function configures the DMA source transfer width according to the
334  * currently set SPI frame size. Therefore, whenever the SPI frame is updated
335  * (using qm_spi_set_config) this function needs to be called again as the
336  * previous source transfer width configuration is no longer valid. Note that if
337  * the current frame size lies between 17 and 24 bits, this function fails
338  * (returning -EINVAL) as the DMA core cannot handle 3-byte source width
339  * transfers with buffers containing 1 padding byte between consecutive frames.
340  *
341  * Note that qm_dma_init() must first be called before configuring a channel.
342  *
343  * @param[in] spi SPI controller identifier.
344  * @param[in] dma_ctrl_id DMA controller identifier.
345  * @param[in] dma_channel_id DMA channel identifier.
346  * @param[in] dma_channel_direction DMA channel direction, either
347  * QM_DMA_MEMORY_TO_PERIPHERAL (TX transfer) or QM_DMA_PERIPHERAL_TO_MEMORY
348  * (RX transfer).
349  *
350  * @return Standard errno return type for QMSI.
351  * @retval 0 on success.
352  * @retval Negative @ref errno for possible error codes.
353  */
355  const qm_spi_t spi, const qm_dma_t dma_ctrl_id,
356  const qm_dma_channel_id_t dma_channel_id,
357  const qm_dma_channel_direction_t dma_channel_direction);
358 
359 /**
360  * Perform a DMA-based transfer on the SPI bus.
361  *
362  * If transfer mode is full duplex (QM_SPI_TMOD_TX_RX), then tx_len and
363  * rx_len must be equal. Similarly, for transmit-only transfers (QM_SPI_TMOD_TX)
364  * rx_len must be 0 while for receive-only transfers (QM_SPI_TMOD_RX) tx_len
365  * must be 0. Transfer length is limited to 4KB.
366  *
367  * For starting a transfer, this controller demands at least one slave
368  * select line (SS) to be enabled. Thus, a call to qm_spi_slave_select()
369  * with one of the four SS valid lines is mandatory. This is true even if
370  * the native slave select line is not used (i.e. when a GPIO is used to
371  * drive the SS signal manually).
372  *
373  * Note that qm_spi_dma_channel_config() must first be called in order to
374  * configure all DMA channels needed for a transfer.
375  *
376  * @param[in] spi SPI controller identifier.
377  * @param[in] xfer Structure containing pre-allocated write and read data
378  * buffers and callback functions. This must not be NULL and
379  * must be kept valid until the transfer is complete.
380  *
381  * @return Standard errno return type for QMSI.
382  * @retval 0 on success.
383  * @retval Negative @ref errno for possible error codes.
384  */
385 int qm_spi_dma_transfer(const qm_spi_t spi,
386  const qm_spi_async_transfer_t *const xfer);
387 
388 /**
389  * Terminate SPI IRQ transfer.
390  *
391  * Terminate the current IRQ transfer on the SPI bus.
392  * This will cause the user callback to be called with
393  * error code set to -ECANCELED.
394  *
395  * @param[in] spi Which SPI to cancel the current transfer.
396  *
397  * @return Standard errno return type for QMSI.
398  * @retval 0 on success.
399  * @retval Negative @ref errno for possible error codes.
400  */
402 
403 /**
404  * Terminate the current DMA transfer on the SPI bus.
405  *
406  * Terminate the current DMA transfer on the SPI bus.
407  * This will cause the relevant callbacks to be invoked.
408  *
409  * @param[in] spi SPI controller identifier.
410  *
411  * @return Standard errno return type for QMSI.
412  * @retval 0 on success.
413  * @retval Negative @ref errno for possible error codes.
414  */
416 
417 /**
418  * Save SPI context.
419  *
420  * Saves the configuration of the specified SPI peripheral
421  * before entering sleep.
422  *
423  * @param[in] spi SPI controller identifier.
424  * @param[out] ctx SPI context structure. This must not be NULL.
425  *
426  * @return Standard errno return type for QMSI.
427  * @retval 0 on success.
428  * @retval Negative @ref errno for possible error codes.
429  */
430 int qm_spi_save_context(const qm_spi_t spi, qm_spi_context_t *const ctx);
431 
432 /**
433  * Restore SPI context.
434  *
435  * Restore the configuration of the specified SPI peripheral
436  * after exiting sleep.
437  *
438  * @param[in] spi SPI controller identifier.
439  * @param[in] ctx SPI context structure. This must not be NULL.
440  *
441  * @return Standard errno return type for QMSI.
442  * @retval 0 on success.
443  * @retval Negative @ref errno for possible error codes.
444  */
445 int qm_spi_restore_context(const qm_spi_t spi,
446  const qm_spi_context_t *const ctx);
447 
448 /**
449  * @}
450  */
451 #endif /* __QM_SPI_H__ */
int qm_spi_set_config(const qm_spi_t spi, const qm_spi_config_t *const cfg)
Set SPI configuration.
Definition: qm_spi.c:423
qm_spi_slave_select_t
SPI slave select type.
Definition: qm_spi.h:81
5 bit frame.
Definition: qm_spi.h:24
qm_spi_frame_size_t
QM SPI frame size type.
Definition: qm_spi.h:22
int qm_spi_irq_transfer(const qm_spi_t spi, volatile const qm_spi_async_transfer_t *const xfer)
Interrupt based transfer on SPI.
Definition: qm_spi.c:639
9 bit frame.
Definition: qm_spi.h:28
int qm_spi_dma_channel_config(const qm_spi_t spi, const qm_dma_t dma_ctrl_id, const qm_dma_channel_id_t dma_channel_id, const qm_dma_channel_direction_t dma_channel_direction)
Configure a DMA channel with a specific transfer direction.
Definition: qm_spi.c:851
int qm_spi_dma_transfer_terminate(const qm_spi_t spi)
Terminate the current DMA transfer on the SPI bus.
Definition: qm_spi.c:1094
18 bit frame.
Definition: qm_spi.h:37
uint16_t tx_len
Number of data frames to write.
Definition: qm_spi.h:148
int qm_spi_transfer(const qm_spi_t spi, const qm_spi_transfer_t *const xfer, qm_spi_status_t *const status)
Multi-frame read / write on SPI.
Definition: qm_spi.c:499
SPI synchronous transfer type.
Definition: qm_spi.h:181
11 bit frame.
Definition: qm_spi.h:30
qm_dma_t
DMA instances.
Definition: qm_soc_regs.h:1480
int qm_spi_slave_select(const qm_spi_t spi, const qm_spi_slave_select_t ss)
Select which slave to perform SPI transmissions on.
Definition: qm_spi.c:465
19 bit frame.
Definition: qm_spi.h:38
Slave Select 3.
Definition: qm_spi.h:86
Clock Polarity = 0, Clock Phase = 1.
Definition: qm_spi.h:69
void * rx
Read data.
Definition: qm_spi.h:147
7 bit frame.
Definition: qm_spi.h:26
Clock Polarity = 1, Clock Phase = 1.
Definition: qm_spi.h:71
20 bit frame.
Definition: qm_spi.h:39
14 bit frame.
Definition: qm_spi.h:33
17 bit frame.
Definition: qm_spi.h:36
void * rx
Read data.
Definition: qm_spi.h:183
Transmit & Receive.
Definition: qm_spi.h:58
SPI context type.
Definition: qm_soc_regs.h:1071
22 bit frame.
Definition: qm_spi.h:41
int qm_spi_irq_transfer_terminate(const qm_spi_t spi)
Terminate SPI IRQ transfer.
Definition: qm_spi.c:736
Appl.
Definition: qm_spi.h:96
13 bit frame.
Definition: qm_spi.h:32
Standard SPI mode.
Definition: qm_spi.h:105
Transmit Only.
Definition: qm_spi.h:59
Receive Only.
Definition: qm_spi.h:60
Clock Polarity = 1, Clock Phase = 0.
Definition: qm_spi.h:70
12 bit frame.
Definition: qm_spi.h:31
bool keep_enabled
Keep device on once transfer is done.
Definition: qm_spi.h:150
qm_spi_t
Number of SPI controllers.
Definition: qm_soc_regs.h:709
31 bit frame.
Definition: qm_spi.h:50
uint16_t tx_len
Number of data frames to write.
Definition: qm_spi.h:184
4 bit frame.
Definition: qm_spi.h:23
qm_spi_status_t
SPI status.
Definition: qm_spi.h:92
int qm_spi_dma_transfer(const qm_spi_t spi, const qm_spi_async_transfer_t *const xfer)
Perform a DMA-based transfer on the SPI bus.
Definition: qm_spi.c:955
32 bit frame.
Definition: qm_spi.h:51
23 bit frame.
Definition: qm_spi.h:42
SPI aynchronous transfer type.
Definition: qm_spi.h:145
qm_spi_tmode_t
SPI transfer mode type.
Definition: qm_spi.h:57
SPI device is busy.
Definition: qm_spi.h:94
Clock Polarity = 0, Clock Phase = 0.
Definition: qm_spi.h:68
28 bit frame.
Definition: qm_spi.h:47
24 bit frame.
Definition: qm_spi.h:43
int qm_spi_save_context(const qm_spi_t spi, qm_spi_context_t *const ctx)
Save SPI context.
Definition: qm_spi.c:1157
8 bit frame.
Definition: qm_spi.h:27
21 bit frame.
Definition: qm_spi.h:40
qm_dma_channel_direction_t
DMA channel direction.
Definition: qm_dma.h:56
26 bit frame.
Definition: qm_spi.h:45
SPI device is not in use.
Definition: qm_spi.h:93
29 bit frame.
Definition: qm_spi.h:48
15 bit frame.
Definition: qm_spi.h:34
qm_spi_bmode_t
SPI bus mode type.
Definition: qm_spi.h:67
void * tx
Write data.
Definition: qm_spi.h:146
Appl.
Definition: qm_spi.h:97
Slave select disable.
Definition: qm_spi.h:82
void * callback_data
Callback user data.
Definition: qm_spi.h:169
10 bit frame.
Definition: qm_spi.h:29
16 bit frame.
Definition: qm_spi.h:35
int qm_spi_get_status(const qm_spi_t spi, qm_spi_status_t *const status)
Get SPI bus status.
Definition: qm_spi.c:479
uint16_t rx_len
Number of data frames to read.
Definition: qm_spi.h:149
qm_spi_frame_format_t
QM SPI Frame Format.
Definition: qm_spi.h:103
int qm_spi_irq_update(const qm_spi_t spi, volatile const qm_spi_async_transfer_t *const xfer, const qm_spi_update_t update)
Update parameters of Interrupt based transfer on SPI.
Definition: qm_spi.c:584
25 bit frame.
Definition: qm_spi.h:44
qm_dma_channel_id_t
DMA channel IDs.
Definition: qm_soc_regs.h:1486
6 bit frame.
Definition: qm_spi.h:25
void * tx
Write data.
Definition: qm_spi.h:182
30 bit frame.
Definition: qm_spi.h:49
27 bit frame.
Definition: qm_spi.h:46
uint16_t rx_len
Number of data frames to read.
Definition: qm_spi.h:185
int qm_spi_restore_context(const qm_spi_t spi, const qm_spi_context_t *const ctx)
Restore SPI context.
Definition: qm_spi.c:1165
Slave Select 2.
Definition: qm_spi.h:85
Slave Select 0.
Definition: qm_spi.h:83
Slave Select 1.
Definition: qm_spi.h:84
RX transfer has overflown.
Definition: qm_spi.h:95
EEPROM Read.
Definition: qm_spi.h:61