8 static void (*callback[QM_PWM_NUM][QM_PWM_ID_NUM])(
void *data,
10 static void *callback_data[QM_PWM_NUM][QM_PWM_ID_NUM];
12 #if (NUM_PWM_CONTROLLER_INTERRUPTS > 1)
13 const uint32_t pwm_isr_vectors[QM_PWM_ID_NUM] = {
14 QM_IRQ_PWM_0_INT_0_PRIORITY, QM_IRQ_PWM_0_INT_1_PRIORITY,
15 QM_IRQ_PWM_0_INT_2_PRIORITY, QM_IRQ_PWM_0_INT_3_PRIORITY};
22 #if (NUM_PWM_CONTROLLER_INTERRUPTS > 1)
32 if (callback[pwm][
id]) {
33 (callback[pwm][id])(callback_data[pwm][
id], BIT(
id));
38 QM_ISR_EOI(pwm_isr_vectors[
id]);
43 pwm_isr_handler(QM_PWM_0, QM_PWM_ID_0);
48 pwm_isr_handler(QM_PWM_0, QM_PWM_ID_1);
53 pwm_isr_handler(QM_PWM_0, QM_PWM_ID_2);
58 pwm_isr_handler(QM_PWM_0, QM_PWM_ID_3);
68 for (; pwm_id < QM_PWM_ID_NUM; pwm_id++) {
69 if (int_status & BIT(pwm_id)) {
70 if (callback[QM_PWM_0][pwm_id]) {
71 (*callback[QM_PWM_0][pwm_id])(
72 callback_data[QM_PWM_0][pwm_id],
78 QM_ISR_EOI(QM_IRQ_PWM_0_INT_VECTOR);
85 QM_CHECK(pwm < QM_PWM_NUM, -EINVAL);
86 QM_CHECK(
id < QM_PWM_ID_NUM, -EINVAL);
96 QM_CHECK(pwm < QM_PWM_NUM, -EINVAL);
97 QM_CHECK(
id < QM_PWM_ID_NUM, -EINVAL);
109 QM_CHECK(pwm < QM_PWM_NUM, -EINVAL);
110 QM_CHECK(
id < QM_PWM_ID_NUM, -EINVAL);
111 QM_CHECK(cfg != NULL, -EINVAL);
112 QM_CHECK(cfg->
mode <= QM_PWM_MODE_PWM, -EINVAL);
113 QM_CHECK(0 < cfg->
lo_count, -EINVAL);
115 QM_CHECK(cfg->
mode == QM_PWM_MODE_PWM ? 0 != cfg->
hi_count : 1,
132 const uint32_t lo_count,
const uint32_t hi_count)
134 QM_CHECK(pwm < QM_PWM_NUM, -EINVAL);
135 QM_CHECK(
id < QM_PWM_ID_NUM, -EINVAL);
136 QM_CHECK(0 < lo_count, -EINVAL);
138 QM_CHECK(((QM_PWM[pwm]->timer[
id].controlreg & QM_PWM_CONF_MODE_MASK) ==
152 uint32_t *
const lo_count, uint32_t *
const hi_count)
154 QM_CHECK(pwm < QM_PWM_NUM, -EINVAL);
155 QM_CHECK(
id < QM_PWM_ID_NUM, -EINVAL);
156 QM_CHECK(lo_count != NULL, -EINVAL);
157 QM_CHECK(hi_count != NULL, -EINVAL);
166 #if (ENABLE_RESTORE_CONTEXT)
169 QM_CHECK(pwm < QM_PWM_NUM, -EINVAL);
170 QM_CHECK(ctx != NULL, -EINVAL);
175 for (i = 0; i < QM_PWM_ID_NUM; i++) {
187 QM_CHECK(pwm < QM_PWM_NUM, -EINVAL);
188 QM_CHECK(ctx != NULL, -EINVAL);
193 for (i = 0; i < QM_PWM_ID_NUM; i++) {
void(* callback)(void *data, uint32_t int_status)
User callback.
uint32_t lo_count
Number of cycles the PWM output is driven low.
int qm_pwm_set(const qm_pwm_t pwm, const qm_pwm_id_t id, const uint32_t lo_count, const uint32_t hi_count)
Set the next period values of a PWM channel.
int qm_pwm_restore_context(const qm_pwm_t pwm, const qm_pwm_context_t *const ctx)
Restore PWM peripheral's context.
void * callback_data
Callback user data.
int qm_pwm_start(const qm_pwm_t pwm, const qm_pwm_id_t id)
Start a PWM/timer channel.
qm_pwm_mode_t mode
Pwm mode.
qm_pwm_channel_t timer[QM_PWM_ID_NUM]
2 Timers.
QM_RW uint32_t loadcount
Load Coun.t.
PWM / Timer register map.
uint32_t loadcount
Load Count 1.
QM PWM / Timer configuration type.
int qm_pwm_set_config(const qm_pwm_t pwm, const qm_pwm_id_t id, const qm_pwm_config_t *const cfg)
Change the configuration of a PWM channel.
QM_RW uint32_t timer_loadcount2[QM_PWM_ID_NUM]
Timer Load Count 2.
QM_RW uint32_t timersintstatus
Timers Interrupt Status.
int qm_pwm_save_context(const qm_pwm_t pwm, qm_pwm_context_t *const ctx)
Save PWM peripheral's context.
bool mask_interrupt
Mask interrupt.
QM_ISR_DECLARE(qm_pwm_0_isr_0)
ISR for PWM 0 Channel 0 interrupt.
int qm_pwm_stop(const qm_pwm_t pwm, const qm_pwm_id_t id)
Stop a PWM/timer channel.
QM_RW uint32_t controlreg
Control.
uint32_t loadcount2
Load Count 2.
QM_RW uint32_t eoi
End Of Interrupt.
qm_pwm_t
Number of PWM / Timer controllers.
int qm_pwm_get(const qm_pwm_t pwm, const qm_pwm_id_t id, uint32_t *const lo_count, uint32_t *const hi_count)
Get the current period values of a PWM channel.
uint32_t hi_count
Number of cycles the PWM output is driven high.
uint32_t controlreg
Control Register.