Intel® Quark™ Microcontroller Software Interface  1.4.0
Intel® Quark™ Microcontroller BSP
ss_clk.h
1 /*
2 * {% copyright %}
3 */
4 
5 #ifndef __SS_CLK_H__
6 #define __SS_CLK_H__
7 
8 #include "qm_common.h"
9 #include "qm_sensor_regs.h"
10 #include "clk.h"
11 
12 /**
13  * Clock Management for Sensor Subsystem.
14  *
15  * The clock distribution has three level of gating:
16  * 1. SE SoC gating through register CCU_PERIPH_CLK_GATE_CTL
17  * 2. SS Soc gating through register IO_CREG_MST0_CTRL (IO_CREG_MST0_CTRL)
18  * 3. SS peripheral clk gating
19  * Note: the first two are ungated by hardware power-on default (clock gating is
20  * done at peripheral level). Thus the only one level of control is enough (and
21  * implemented in ss_clk driver) to gate clock on or off to the particular
22  * peripheral.
23  *
24  * @defgroup groupSSClock SS Clock
25  * @{
26  */
27 
28 /**
29  * Peripheral clocks selection type.
30  */
31 typedef enum {
32  SS_CLK_PERIPH_ADC = BIT(31), /**< ADC clock selector. */
33  SS_CLK_PERIPH_I2C_1 = BIT(30), /**< I2C 1 clock selector. */
34  SS_CLK_PERIPH_I2C_0 = BIT(29), /**< I2C 0 clock selector. */
35  SS_CLK_PERIPH_SPI_1 = BIT(28), /**< SPI 1 clock selector. */
36  SS_CLK_PERIPH_SPI_0 = BIT(27), /**< SPI 0 clock selector. */
37 
38  /**
39  * GPIO 1 clock selector.
40  *
41  * Special domain peripherals - these do not map onto the standard
42  * register.
43  */
45  /**
46  * GPIO 0 clock selector.
47  *
48  * Special domain peripherals - these do not map onto the standard
49  * register.
50  */
53 
54 /**
55  * Enable clocking for SS GPIO peripheral.
56  *
57  * @param [in] gpio GPIO port index.
58  *
59  * @return Standard errno return type for QMSI.
60  * @retval 0 on success.
61  * @retval Negative @ref errno for possible error codes.
62  */
63 int ss_clk_gpio_enable(const qm_ss_gpio_t gpio);
64 
65 /**
66  * Disable clocking for SS GPIO peripheral.
67  *
68  * @param [in] gpio GPIO port index.
69  *
70  * @return Standard errno return type for QMSI.
71  * @retval 0 on success.
72  * @retval Negative @ref errno for possible error codes.
73  */
74 int ss_clk_gpio_disable(const qm_ss_gpio_t gpio);
75 
76 /**
77  * Enable clocking for SS SPI peripheral.
78  *
79  * @param [in] spi SPI port index.
80  *
81  * @return Standard errno return type for QMSI.
82  * @retval 0 on success.
83  * @retval Negative @ref errno for possible error codes.
84  */
85 int ss_clk_spi_enable(const qm_ss_spi_t spi);
86 
87 /**
88  * Disable clocking for SS SPI peripheral.
89  *
90  * @param [in] spi SPI port index.
91  *
92  * @return Standard errno return type for QMSI.
93  * @retval 0 on success.
94  * @retval Negative @ref errno for possible error codes.
95  */
96 int ss_clk_spi_disable(const qm_ss_spi_t spi);
97 
98 /**
99  * Enable clocking for SS I2C peripheral.
100  *
101  * @param [in] i2c I2C port index.
102  *
103  * @return Standard errno return type for QMSI.
104  * @retval 0 on success.
105  * @retval Negative @ref errno for possible error codes.
106  */
107 int ss_clk_i2c_enable(const qm_ss_i2c_t i2c);
108 
109 /**
110  * Disable clocking for SS I2C peripheral.
111  *
112  * @param [in] i2c I2C port index.
113  *
114  * @return Standard errno return type for QMSI.
115  * @retval 0 on success.
116  * @retval Negative @ref errno for possible error codes.
117  */
118 int ss_clk_i2c_disable(const qm_ss_i2c_t i2c);
119 
120 /**
121  * Enable the SS ADC clock.
122  *
123  * @return Standard errno return type for QMSI.
124  * @retval 0 on success.
125  */
126 int ss_clk_adc_enable(void);
127 
128 /**
129  * Disable the SS ADC clock.
130  *
131  * @return Standard errno return type for QMSI.
132  * @retval 0 on success.
133  */
134 int ss_clk_adc_disable(void);
135 
136 /**
137  * Set clock divisor for SS ADC.
138  *
139  * Note: If the system clock speed is changed, the divisor must be recalculated.
140  * The minimum supported speed for the SS ADC is 0.14 MHz. So for a system clock
141  * speed of 1 MHz, the max value of div is 7, and for 32 MHz, the max value is
142  * 224. System clock speeds of less than 1 MHz are not supported by this
143  * function.
144  *
145  * @param [in] div ADC clock divider value.
146  *
147  * @return Standard errno return type for QMSI.
148  * @retval 0 on success.
149  * @retval Negative @ref errno for possible error codes.
150  */
151 int ss_clk_adc_set_div(const uint32_t div);
152 
153 /**
154  * @}
155  */
156 
157 #endif /* __SS_CLK_H__ */
int ss_clk_spi_enable(const qm_ss_spi_t spi)
Enable clocking for SS SPI peripheral.
Definition: ss_clk.c:28
int ss_clk_gpio_enable(const qm_ss_gpio_t gpio)
Enable clocking for SS GPIO peripheral.
Definition: ss_clk.c:8
I2C 1 clock selector.
Definition: ss_clk.h:33
GPIO 0 clock selector.
Definition: ss_clk.h:51
qm_ss_gpio_t
Sensor Subsystem GPIO.
int ss_clk_i2c_disable(const qm_ss_i2c_t i2c)
Disable clocking for SS I2C peripheral.
Definition: ss_clk.c:52
qm_ss_i2c_t
Sensor Subsystem I2C.
I2C 0 clock selector.
Definition: ss_clk.h:34
int ss_clk_adc_set_div(const uint32_t div)
Set clock divisor for SS ADC.
Definition: ss_clk.c:76
SPI 1 clock selector.
Definition: ss_clk.h:35
int ss_clk_adc_disable(void)
Disable the SS ADC clock.
Definition: ss_clk.c:68
SPI 0 clock selector.
Definition: ss_clk.h:36
ss_clk_periph_t
Peripheral clocks selection type.
Definition: ss_clk.h:31
GPIO 1 clock selector.
Definition: ss_clk.h:44
int ss_clk_spi_disable(const qm_ss_spi_t spi)
Disable clocking for SS SPI peripheral.
Definition: ss_clk.c:36
int ss_clk_gpio_disable(const qm_ss_gpio_t gpio)
Disable clocking for SS GPIO peripheral.
Definition: ss_clk.c:19
int ss_clk_i2c_enable(const qm_ss_i2c_t i2c)
Enable clocking for SS I2C peripheral.
Definition: ss_clk.c:44
ADC clock selector.
Definition: ss_clk.h:32
qm_ss_spi_t
Sensor Subsystem SPI modules.
int ss_clk_adc_enable(void)
Enable the SS ADC clock.
Definition: ss_clk.c:60