6 #include "qm_interrupt.h"
16 #include "qm_ss_interrupt.h"
17 #include "qm_sensor_regs.h"
20 static void ss_register_irq(
unsigned int vector);
23 #error "Unsupported / unspecified processor detected."
29 #define X86_FLAGS_IF BIT(9)
36 __asm__ __volatile__(
"cli");
45 __asm__ __volatile__(
"sti");
58 __asm__ __volatile__(
"clri %0" :
"=r"(key));
69 __asm__ __volatile__(
"seti %0" : :
"ir"(key));
82 __asm__ __volatile__(
"pushfl;\n\t"
98 if (!(key & X86_FLAGS_IF)) {
107 __asm__ __volatile__(
"sti;\n\t" : :);
114 ioapic_mask_irq(irq);
128 ioapic_unmask_irq(irq);
131 mvic_unmask_irq(irq);
139 #if (ENABLE_RESTORE_CONTEXT)
146 QM_CHECK(ctx != NULL, -EINVAL);
148 for (irq = 0; irq < QM_IOAPIC_NUM_RTES; irq++) {
149 rte_low = _ioapic_get_redtbl_entry_lo(irq);
161 QM_CHECK(ctx != NULL, -EINVAL);
165 for (irq = 0; irq < QM_IOAPIC_NUM_RTES; irq++) {
167 _ioapic_set_redtbl_entry_lo(irq, rte_low);
178 QM_CHECK(ctx != NULL, -EINVAL);
184 for (i = 0; i < (QM_SS_INT_VECTOR_NUM - QM_SS_EXCEPTION_NUM); i++) {
185 __builtin_arc_sr(i + QM_SS_EXCEPTION_NUM, QM_SS_AUX_IRQ_SELECT);
187 ctx->
irq_config[i] = __builtin_arc_lr(QM_SS_AUX_IRQ_PRIORITY)
189 ctx->
irq_config[i] |= __builtin_arc_lr(QM_SS_AUX_IRQ_TRIGGER)
191 ctx->
irq_config[i] |= __builtin_arc_lr(QM_SS_AUX_IRQ_ENABLE);
194 status32 = __builtin_arc_lr(QM_SS_AUX_STATUS32);
198 ctx->
irq_ctrl = __builtin_arc_lr(QM_SS_AUX_IRQ_CTRL);
208 QM_CHECK(ctx != NULL, -EINVAL);
210 for (i = 0; i < (QM_SS_INT_VECTOR_NUM - QM_SS_EXCEPTION_NUM); i++) {
211 __builtin_arc_sr(i + QM_SS_EXCEPTION_NUM, QM_SS_AUX_IRQ_SELECT);
214 QM_SS_AUX_IRQ_PRIORITY);
215 __builtin_arc_sr((ctx->
irq_config[i] >> 1) & BIT(0),
216 QM_SS_AUX_IRQ_TRIGGER);
218 QM_SS_AUX_IRQ_ENABLE);
221 __builtin_arc_sr(ctx->
irq_ctrl, QM_SS_AUX_IRQ_CTRL);
224 reg = __builtin_arc_lr(QM_SS_AUX_STATUS32);
229 __builtin_arc_kflag(reg);
250 void _qm_irq_setup(uint32_t irq)
257 ioapic_register_irq(irq, QM_IRQ_TO_VECTOR(irq));
258 ioapic_unmask_irq(irq);
260 mvic_register_irq(irq);
261 mvic_unmask_irq(irq);
263 ss_register_irq(QM_IRQ_TO_VECTOR(irq));
276 void _qm_register_isr(uint32_t vector,
qm_isr_t isr)
281 __builtin_arc_sr((uint32_t)&__ivt_vect_table[0] + (vector * 4),
289 __ivt_vect_table[vector] = isr;
291 idt_set_intr_gate_desc(vector, (uint32_t)isr);
296 static void ss_register_irq(
unsigned int vector)
304 case QM_SS_IRQ_ADC_0_PWR_INT_VECTOR:
305 case QM_IRQ_RTC_0_INT_VECTOR:
306 case QM_IRQ_AONPT_0_INT_VECTOR:
307 case QM_IRQ_WDT_0_INT_VECTOR:
309 __builtin_arc_sr(vector, QM_SS_AUX_IRQ_SELECT);
310 __builtin_arc_sr(QM_SS_IRQ_EDGE_SENSITIVE,
311 QM_SS_AUX_IRQ_TRIGGER);
uint32_t status32_irq_threshold
STATUS32 Interrupt Threshold.
void(* qm_ss_isr_t)(struct interrupt_frame *frame)
Interrupt service routine type.
void qm_irq_unlock(unsigned int key)
Restore previous interrupt state on the CPU saved via qm_irq_lock().
void qm_irq_unmask(uint32_t irq)
Unmask a given interrupt line.
unsigned int qm_irq_lock(void)
Save interrupt state and disable all interrupts on the CPU.
void(* qm_isr_t)(struct interrupt_frame *frame)
Interrupt service routine type.
void qm_irq_disable(void)
Unconditionally disable interrupt delivery on the CPU.
void qm_ss_irq_enable(void)
Enable interrupt delivery for the Sensor Subsystem.
uint32_t irq_ctrl
Interrupt Context Saving Control Register.
uint32_t status32_irq_enable
STATUS32 Interrupt Enable.
void qm_ss_irq_disable(void)
Disable interrupt delivery for the Sensor Subsystem.
void qm_irq_mask(uint32_t irq)
Mask a given interrupt line.
void qm_irq_enable(void)
Unconditionally enable interrupt delivery on the CPU.
uint32_t redtbl_entries[QM_IOAPIC_NUM_RTES]
Redirection Table Entries.
void qm_ss_irq_mask(uint32_t irq)
Mask a given interrupt line.
uint8_t irq_config[QM_SS_INT_VECTOR_NUM-QM_SS_EXCEPTION_NUM]
IRQ configuration:
void qm_ss_irq_unmask(uint32_t irq)
Unmask a given interrupt line.