5 #ifndef __REGISTERS_H__
6 #define __REGISTERS_H__
9 #include "qm_soc_interrupts.h"
10 #include "qm_interrupt_router_regs.h"
11 #include "flash_layout.h"
21 #define HAS_4_TIMERS (1)
22 #define HAS_AON_GPIO (1)
23 #define HAS_MAILBOX (1)
26 #if !defined(QM_SENSOR)
37 QM_RW uint32_t osc0_cfg0;
38 QM_RW uint32_t osc0_stat1;
39 QM_RW uint32_t osc0_cfg1;
40 QM_RW uint32_t osc1_stat0;
41 QM_RW uint32_t osc1_cfg0;
44 ccu_periph_clk_gate_ctl;
46 ccu_periph_clk_div_ctl0;
53 QM_RW uint32_t ccu_lp_clk_ctl;
54 QM_RW uint32_t reserved;
55 QM_RW uint32_t ccu_mlayer_ahb_ctl;
56 QM_RW uint32_t ccu_sys_clk_ctl;
57 QM_RW uint32_t osc_lock_0;
62 #define QM_SCSS_CCU ((qm_scss_ccu_reg_t *)(&test_scss_ccu))
65 #define QM_SCSS_CCU_BASE (0xB0800000)
66 #define QM_SCSS_CCU ((qm_scss_ccu_reg_t *)QM_SCSS_CCU_BASE)
70 #define QM_OSC0_MODE_SEL BIT(3)
71 #define QM_OSC0_PD BIT(2)
72 #define QM_OSC1_PD BIT(1)
75 #define QM_OSC0_EN_CRYSTAL BIT(0)
78 #define OSC0_CFG1_OSC0_FADJ_XTAL_MASK (0x000F0000)
79 #define OSC0_CFG1_OSC0_FADJ_XTAL_OFFS (16)
80 #define OSC0_CFG0_OSC0_XTAL_COUNT_VALUE_MASK (0x00600000)
81 #define OSC0_CFG0_OSC0_XTAL_COUNT_VALUE_OFFS (21)
84 #define OSC0_CFG1_FTRIMOTP_MASK (0x3FF00000)
85 #define OSC0_CFG1_FTRIMOTP_OFFS (20)
86 #define OSC0_CFG1_SI_FREQ_SEL_MASK (0x00000300)
87 #define OSC0_CFG1_SI_FREQ_SEL_OFFS (8)
89 #define QM_OSC0_MODE_SEL BIT(3)
90 #define QM_OSC0_LOCK_SI BIT(0)
91 #define QM_OSC0_LOCK_XTAL BIT(1)
92 #define QM_OSC0_EN_SI_OSC BIT(1)
94 #define QM_SI_OSC_1V2_MODE BIT(0)
97 #define QM_CCU_PERIPH_PCLK_DIV_OFFSET (1)
98 #define QM_CCU_PERIPH_PCLK_DIV_EN BIT(0)
101 #define QM_CCU_MLAYER_AHB_CTL (REG_VAL(0xB0800034))
104 #define QM_CCU_SYS_CLK_SEL BIT(0)
105 #define QM_SCSS_CCU_SYS_CLK_SEL BIT(0)
106 #define QM_SCSS_CCU_C2_LP_EN BIT(1)
107 #define QM_SCSS_CCU_SS_LPS_EN BIT(0)
108 #define QM_CCU_RTC_CLK_EN BIT(1)
109 #define QM_CCU_RTC_CLK_DIV_EN BIT(2)
110 #define QM_CCU_SYS_CLK_DIV_EN BIT(7)
111 #define QM_CCU_SYS_CLK_DIV_MASK (0x00000300)
113 #define QM_OSC0_SI_FREQ_SEL_DEF_MASK (0xFFFFFCFF)
114 #define QM_CCU_GPIO_DB_DIV_OFFSET (2)
115 #define QM_CCU_GPIO_DB_CLK_DIV_EN BIT(1)
116 #define QM_CCU_GPIO_DB_CLK_EN BIT(0)
117 #define QM_CCU_RTC_CLK_DIV_OFFSET (3)
118 #define QM_CCU_SYS_CLK_DIV_OFFSET (8)
119 #define QM_CCU_DMA_CLK_EN BIT(6)
134 QM_RW uint32_t reserved;
139 QM_RW uint32_t reserved1;
142 QM_RW uint32_t wo_sp;
149 #define QM_SCSS_GP ((qm_scss_gp_reg_t *)(&test_scss_gp))
152 #define QM_SCSS_GP_BASE (0xB0800100)
153 #define QM_SCSS_GP ((qm_scss_gp_reg_t *)QM_SCSS_GP_BASE)
157 #define QM_GPS0_BIT_FM (0)
158 #define QM_GPS0_BIT_X86_WAKEUP (1)
159 #define QM_GPS0_BIT_SENSOR_WAKEUP (2)
175 #define QM_SCSS_MEM ((qm_scss_mem_reg_t *)(&test_scss_mem))
178 #define QM_SCSS_MEM_BASE (0xB0800200)
179 #define QM_SCSS_MEM ((qm_scss_mem_reg_t *)QM_SCSS_MEM_BASE)
191 QM_RW uint32_t cmp_en;
192 QM_RW uint32_t cmp_ref_sel;
195 QM_RW uint32_t cmp_pwr;
196 QM_RW uint32_t reserved[6];
197 QM_RW uint32_t cmp_stat_clr;
202 #define QM_SCSS_CMP ((qm_scss_cmp_reg_t *)(&test_scss_cmp))
205 #define QM_SCSS_CMP_BASE (0xB0800300)
206 #define QM_SCSS_CMP ((qm_scss_cmp_reg_t *)QM_SCSS_CMP_BASE)
209 #define QM_AC_HP_COMPARATORS_MASK (0x7FFC0)
220 QM_RW uint32_t pad[3];
225 QM_RW apic_reg_pad_t reserved0[2];
226 QM_RW apic_reg_pad_t
id;
228 QM_RW apic_reg_pad_t reserved1[4];
237 QM_RW apic_reg_pad_t isr[8];
238 QM_RW apic_reg_pad_t tmr[8];
239 QM_RW apic_reg_pad_t irr[8];
241 QM_RW apic_reg_pad_t reserved2[6];
243 QM_RW apic_reg_pad_t icr[2];
252 QM_RW apic_reg_pad_t reserved3[4];
261 #define QM_IOAPIC_NUM_RTES (32)
272 uint32_t redtbl_entries[QM_IOAPIC_NUM_RTES];
291 #define QM_LAPIC ((qm_lapic_reg_t *)(&test_lapic))
295 #define QM_LAPIC_BASE (0xFEE00000)
296 #define QM_LAPIC ((qm_lapic_reg_t *)QM_LAPIC_BASE)
299 #define QM_INT_CONTROLLER QM_LAPIC
306 #if defined(ENABLE_EXTERNAL_ISR_HANDLING) || defined(QM_SENSOR)
307 #define QM_ISR_EOI(vector)
309 #define QM_ISR_EOI(vector) \
311 QM_INT_CONTROLLER->eoi.reg = 0; \
312 QM_IOAPIC->eoi.reg = vector; \
317 QM_RW apic_reg_pad_t ioregsel;
318 QM_RW apic_reg_pad_t iowin;
319 QM_RW apic_reg_pad_t reserved[2];
320 QM_RW apic_reg_pad_t eoi;
323 #define QM_IOAPIC_REG_VER (0x01)
324 #define QM_IOAPIC_REG_REDTBL (0x10)
327 qm_ioapic_reg_t test_ioapic;
328 #define QM_IOAPIC ((qm_ioapic_reg_t *)(&test_ioapic))
332 #define QM_IOAPIC_BASE (0xFEC00000)
333 #define QM_IOAPIC ((qm_ioapic_reg_t *)QM_IOAPIC_BASE)
346 QM_RW uint32_t reserved[4];
348 QM_RW uint32_t reserved1[9];
349 QM_RW uint32_t aon_vr;
356 QM_RW uint32_t pm_wait;
357 QM_RW uint32_t reserved2;
358 QM_RW uint32_t p_sts;
359 QM_RW uint32_t reserved3[3];
362 QM_RW uint32_t reserved4[6];
364 QM_RW uint32_t pm_lock;
369 #define QM_SCSS_PMU ((qm_scss_pmu_reg_t *)(&test_scss_pmu))
372 #define QM_SCSS_PMU_BASE (0xB0800504)
373 #define QM_SCSS_PMU ((qm_scss_pmu_reg_t *)QM_SCSS_PMU_BASE)
376 #define QM_SS_CFG_ARC_RUN_REQ_A BIT(24)
377 #define QM_P_STS_HALT_INTERRUPT_REDIRECTION BIT(26)
378 #define QM_P_STS_ARC_HALT BIT(14)
380 #define QM_AON_VR_VSEL_MASK (0xFFE0)
381 #define QM_AON_VR_VSEL_1V2 (0x8)
382 #define QM_AON_VR_VSEL_1V35 (0xB)
383 #define QM_AON_VR_VSEL_1V8 (0x10)
384 #define QM_AON_VR_EN BIT(7)
385 #define QM_AON_VR_VSTRB BIT(5)
387 #define QM_SCSS_SLP_CFG_LPMODE_EN BIT(8)
388 #define QM_SCSS_SLP_CFG_RTC_DIS BIT(7)
389 #define QM_SCSS_PM1C_SLPEN BIT(13)
390 #define QM_SCSS_HOST_VR_EN BIT(7)
391 #define QM_SCSS_PLAT3P3_VR_EN BIT(7)
392 #define QM_SCSS_PLAT1P8_VR_EN BIT(7)
393 #define QM_SCSS_HOST_VR_VREG_SEL BIT(6)
394 #define QM_SCSS_PLAT3P3_VR_VREG_SEL BIT(6)
395 #define QM_SCSS_PLAT1P8_VR_VREG_SEL BIT(6)
396 #define QM_SCSS_VR_ROK BIT(10)
397 #define QM_SCSS_VR_EN BIT(7)
398 #define QM_SCSS_VR_VREG_SEL BIT(6)
415 #define QM_SCSS_SS ((qm_scss_ss_reg_t *)(&test_scss_ss))
418 #define QM_SCSS_SS_BASE (0xB0800600)
419 #define QM_SCSS_SS ((qm_scss_ss_reg_t *)QM_SCSS_SS_BASE)
422 #define QM_SS_STS_HALT_INTERRUPT_REDIRECTION BIT(26)
436 QM_RW uint32_t aonc_cnt;
437 QM_RW uint32_t aonc_cfg;
438 QM_RW uint32_t aonpt_cnt;
441 QM_RW uint32_t aonpt_ctrl;
447 #define qm_aonc_context_t uint8_t
449 #define HAS_AONPT_BUSY_BIT (0)
451 #define QM_AONC_ENABLE (BIT(0))
452 #define QM_AONC_DISABLE (~QM_AONC_ENABLE)
454 #define QM_AONPT_INTERRUPT (BIT(0))
456 #define QM_AONPT_CLR (BIT(0))
457 #define QM_AONPT_RST (BIT(1))
464 #define QM_AONC test_aonc
468 #define QM_AONC_0_BASE (0xB0800700)
469 #define QM_AONC qm_aonc
482 QM_RW uint32_t periph_cfg0;
483 QM_RW uint32_t reserved[2];
484 QM_RW uint32_t cfg_lock;
489 #define QM_SCSS_PERIPHERAL ((qm_scss_peripheral_reg_t *)(&test_scss_peripheral))
492 #define QM_SCSS_PERIPHERAL_BASE (0xB0800800)
493 #define QM_SCSS_PERIPHERAL ((qm_scss_peripheral_reg_t *)QM_SCSS_PERIPHERAL_BASE)
497 #define QM_SCSS_CFG_LOCK_PROT_RANGE_LOCK BIT(10)
508 QM_RW uint32_t pmux_pullup[4];
509 QM_RW uint32_t pmux_slew[4];
510 QM_RW uint32_t pmux_in_en[4];
511 QM_RW uint32_t pmux_sel[5];
512 QM_RW uint32_t reserved[2];
513 QM_RW uint32_t pmux_pullup_lock;
514 QM_RW uint32_t pmux_slew_lock;
515 QM_RW uint32_t pmux_sel_lock[3];
516 QM_RW uint32_t pmux_in_en_lock;
521 #define QM_SCSS_PMUX ((qm_scss_pmux_reg_t *)(&test_scss_pmux))
524 #define QM_SCSS_PMUX_BASE (0xB0800900)
525 #define QM_SCSS_PMUX ((qm_scss_pmux_reg_t *)QM_SCSS_PMUX_BASE)
529 #define QM_PMUX_SLEW_4MA_DRIVER (0xFFFFFFFF)
530 #define QM_PMUX_SLEW0 (REG_VAL(0xB0800910))
531 #define QM_PMUX_SLEW1 (REG_VAL(0xB0800914))
532 #define QM_PMUX_SLEW2 (REG_VAL(0xB0800918))
533 #define QM_PMUX_SLEW3 (REG_VAL(0xB080091C))
549 #define QM_SCSS_INFO ((qm_scss_info_reg_t *)(&test_scss_info))
552 #define QM_SCSS_INFO_BASE (0xB0801000)
553 #define QM_SCSS_INFO ((qm_scss_info_reg_t *)QM_SCSS_INFO_BASE)
563 #define HAS_MAILBOX (1)
564 #define NUM_MAILBOXES (8)
566 #define HAS_MAILBOX_LAKEMONT_DEST (1)
567 #define HAS_MAILBOX_SENSOR_SUB_SYSTEM_DEST (1)
575 #define QM_MBOX_CH_CTRL_INT BIT(31)
576 #define QM_MBOX_CH_CTRL_MASK (0x7FFFFFFF)
577 #define QM_MBOX_CH_CTRL_SHIFT (0)
594 #define QM_MBOX_CH_STS_CTRL_INT BIT(1)
595 #define QM_MBOX_CH_STS BIT(0)
597 #define QM_MBOX_STATUS_MASK (QM_MBOX_CH_STS | QM_MBOX_CH_STS_CTRL_INT)
605 #define QM_MBOX_CHALL_STS(N) BIT((N * 2))
606 #define QM_MBOX_CHALL_INT_STS(N) BIT((N * 2) + 1)
624 #define QM_MBOX_SS_HALT_MASK_OFFSET (24)
625 #define QM_MBOX_SS_HALT_MASK_MASK (0xFF000000)
626 #define QM_MBOX_HOST_HALT_MASK_OFFSET (16)
627 #define QM_MBOX_HOST_HALT_MASK_MASK (0x00FF0000)
628 #define QM_MBOX_SS_MASK_OFFSET (8)
629 #define QM_MBOX_SS_MASK_MASK (0x0000FF00)
630 #define QM_MBOX_HOST_MASK_OFFSET (0)
631 #define QM_MBOX_HOST_MASK_MASK (0x000000FF)
636 QM_RW uint32_t ch_data[4];
648 #define QM_MAILBOX ((qm_mailbox_reg_t *)(&test_mailbox))
651 #define QM_MAILBOX_BASE (0xB0800A00)
652 #define QM_MAILBOX ((qm_mailbox_reg_t *)QM_MAILBOX_BASE)
663 typedef enum { QM_PWM_0 = 0, QM_PWM_NUM }
qm_pwm_t;
676 QM_RW uint32_t loadcount;
677 QM_RW uint32_t currentvalue;
678 QM_RW uint32_t controlreg;
680 QM_RW uint32_t intstatus;
686 QM_RW uint32_t reserved[20];
687 QM_RW uint32_t timersintstatus;
688 QM_RW uint32_t timerseoi;
689 QM_RW uint32_t timersrawintstatus;
690 QM_RW uint32_t timerscompversion;
692 timer_loadcount2[QM_PWM_ID_NUM];
707 } channel[QM_PWM_ID_NUM];
713 #define QM_PWM test_pwm
718 #define QM_PWM_BASE (0xB0000800)
720 #define QM_PWM qm_pwm
723 #define PWM_START (1)
725 #define QM_PWM_CONF_MODE_MASK (0xA)
726 #define QM_PWM_CONF_INT_EN_MASK (0x4)
728 #define QM_PWM_INTERRUPT_MASK_OFFSET (0x2)
730 #define NUM_PWM_CONTROLLER_INTERRUPTS (1)
748 #define QM_PWM_TIMERNCONTROLREG_TIMER_ENABLE (BIT(0))
749 #define QM_PWM_TIMERNCONTROLREG_TIMER_MODE (BIT(1))
750 #define QM_PWM_TIMERNCONTROLREG_TIMER_INTERRUPT_MASK (BIT(2))
751 #define QM_PWM_TIMERNCONTROLREG_TIMER_PWM (BIT(3))
753 #define QM_PWM_MODE_TIMER_FREE_RUNNING_VALUE (0)
754 #define QM_PWM_MODE_TIMER_COUNT_VALUE (QM_PWM_TIMERNCONTROLREG_TIMER_MODE)
755 #define QM_PWM_MODE_PWM_VALUE \
756 (QM_PWM_TIMERNCONTROLREG_TIMER_PWM | QM_PWM_TIMERNCONTROLREG_TIMER_MODE)
766 typedef enum { QM_WDT_0 = 0, QM_WDT_NUM }
qm_wdt_t;
770 QM_RW uint32_t wdt_cr;
771 QM_RW uint32_t wdt_torr;
772 QM_RW uint32_t wdt_ccvr;
773 QM_RW uint32_t wdt_crr;
774 QM_RW uint32_t wdt_stat;
775 QM_RW uint32_t wdt_eoi;
776 QM_RW uint32_t wdt_comp_param_5;
777 QM_RW uint32_t wdt_comp_param_4;
778 QM_RW uint32_t wdt_comp_param_3;
779 QM_RW uint32_t wdt_comp_param_2;
782 QM_RW uint32_t wdt_comp_version;
783 QM_RW uint32_t wdt_comp_type;
801 #define QM_WDT test_wdt
806 #define QM_WDT_0_BASE (0xB0000000)
809 #define QM_WDT qm_wdt
813 #define QM_WDT_CR_WDT_ENABLE (BIT(0))
815 #define QM_WDT_CR_RMOD (BIT(1))
817 #define QM_WDT_CR_RMOD_OFFSET (1)
819 #define QM_WDT_TORR_TOP_MASK (0xF)
821 #define QM_WDT_RELOAD_VALUE (0x76)
823 #define NUM_WDT_CONTROLLERS (1)
825 #define HAS_WDT_PAUSE (0)
827 #define HAS_SW_SOCWATCH (1)
829 #define QM_WDT_CLOCK_EN_MASK (BIT(1))
831 #define HAS_WDT_CLOCK_ENABLE (1)
866 #define QM_UART_LCR_BREAK BIT(6)
868 #define QM_UART_LCR_DLAB BIT(7)
871 #define QM_UART_MCR_RTS BIT(1)
873 #define QM_UART_MCR_LOOPBACK BIT(4)
875 #define QM_UART_MCR_AFCE BIT(5)
878 #define QM_UART_FCR_FIFOE BIT(0)
880 #define QM_UART_FCR_RFIFOR BIT(1)
882 #define QM_UART_FCR_XFIFOR BIT(2)
885 #define QM_UART_FCR_DEFAULT_TX_RX_THRESHOLD (0xB0)
887 #define QM_UART_FCR_TX_0_RX_1_2_THRESHOLD (0x80)
890 #define QM_UART_IIR_THR_EMPTY (0x02)
892 #define QM_UART_IIR_RECV_DATA_AVAIL (0x04)
894 #define QM_UART_IIR_RECV_LINE_STATUS (0x06)
896 #define QM_UART_IIR_CHAR_TIMEOUT (0x0C)
898 #define QM_UART_IIR_IID_MASK (0x0F)
901 #define QM_UART_LSR_DR BIT(0)
903 #define QM_UART_LSR_OE BIT(1)
905 #define QM_UART_LSR_PE BIT(2)
907 #define QM_UART_LSR_FE BIT(3)
909 #define QM_UART_LSR_BI BIT(4)
911 #define QM_UART_LSR_THRE BIT(5)
913 #define QM_UART_LSR_TEMT BIT(6)
915 #define QM_UART_LSR_RFE BIT(7)
918 #define QM_UART_IER_ERBFI BIT(0)
920 #define QM_UART_IER_ETBEI BIT(1)
922 #define QM_UART_IER_ELSI BIT(2)
924 #define QM_UART_IER_PTIME BIT(7)
927 #define QM_UART_LSR_ERROR_BITS \
928 (QM_UART_LSR_OE | QM_UART_LSR_PE | QM_UART_LSR_FE | QM_UART_LSR_BI)
931 #define QM_UART_FIFO_DEPTH (16)
933 #define QM_UART_FIFO_HALF_DEPTH (QM_UART_FIFO_DEPTH / 2)
936 #define QM_UART_CFG_BAUD_DLH_OFFS 16
938 #define QM_UART_CFG_BAUD_DLL_OFFS 8
940 #define QM_UART_CFG_BAUD_DLF_OFFS 0
942 #define QM_UART_CFG_BAUD_DLH_MASK (0xFF << QM_UART_CFG_BAUD_DLH_OFFS)
944 #define QM_UART_CFG_BAUD_DLL_MASK (0xFF << QM_UART_CFG_BAUD_DLL_OFFS)
946 #define QM_UART_CFG_BAUD_DLF_MASK (0xFF << QM_UART_CFG_BAUD_DLF_OFFS)
949 #define QM_UART_CFG_BAUD_DL_PACK(dlh, dll, dlf) \
950 (dlh << QM_UART_CFG_BAUD_DLH_OFFS | dll << QM_UART_CFG_BAUD_DLL_OFFS | \
951 dlf << QM_UART_CFG_BAUD_DLF_OFFS)
954 #define QM_UART_CFG_BAUD_DLH_UNPACK(packed) \
955 ((packed & QM_UART_CFG_BAUD_DLH_MASK) >> QM_UART_CFG_BAUD_DLH_OFFS)
957 #define QM_UART_CFG_BAUD_DLL_UNPACK(packed) \
958 ((packed & QM_UART_CFG_BAUD_DLL_MASK) >> QM_UART_CFG_BAUD_DLL_OFFS)
960 #define QM_UART_CFG_BAUD_DLF_UNPACK(packed) \
961 ((packed & QM_UART_CFG_BAUD_DLF_MASK) >> QM_UART_CFG_BAUD_DLF_OFFS)
964 typedef enum { QM_UART_0 = 0, QM_UART_1, QM_UART_NUM }
qm_uart_t;
968 QM_RW uint32_t rbr_thr_dll;
969 QM_RW uint32_t ier_dlh;
970 QM_RW uint32_t iir_fcr;
976 QM_RW uint32_t reserved[23];
978 QM_RW uint32_t reserved1[9];
980 QM_RW uint32_t dmasa;
981 QM_RW uint32_t reserved2[5];
983 QM_RW uint32_t padding[0xCF];
1007 #define QM_UART test_uart
1011 #define QM_UART_0_BASE (0xB0002000)
1012 #define QM_UART_1_BASE (0xB0002400)
1015 #define QM_UART qm_uart
1035 QM_RW uint32_t ctrlr0;
1036 QM_RW uint32_t ctrlr1;
1037 QM_RW uint32_t ssienr;
1038 QM_RW uint32_t mwcr;
1040 QM_RW uint32_t baudr;
1041 QM_RW uint32_t txftlr;
1042 QM_RW uint32_t rxftlr;
1043 QM_RW uint32_t txflr;
1044 QM_RW uint32_t rxflr;
1048 QM_RW uint32_t risr;
1049 QM_RW uint32_t txoicr;
1050 QM_RW uint32_t rxoicr;
1051 QM_RW uint32_t rxuicr;
1052 QM_RW uint32_t msticr;
1054 QM_RW uint32_t dmacr;
1055 QM_RW uint32_t dmatdlr;
1056 QM_RW uint32_t dmardlr;
1058 QM_RW uint32_t ssi_comp_version;
1059 QM_RW uint32_t dr[36];
1060 QM_RW uint32_t rx_sample_dly;
1061 QM_RW uint32_t padding[0xC4];
1081 #define QM_SPI test_spi_controllers
1085 #define QM_SPI_MST_0_BASE (0xB0001000)
1086 #define QM_SPI_MST_1_BASE (0xB0001400)
1088 #define QM_SPI qm_spi_controllers
1091 #define QM_SPI_SLV_BASE (0xB0001800)
1095 #define QM_SPI_CTRLR0_DFS_32_MASK (0x001F0000)
1096 #define QM_SPI_CTRLR0_TMOD_MASK (0x00000300)
1097 #define QM_SPI_CTRLR0_SCPOL_SCPH_MASK (0x000000C0)
1098 #define QM_SPI_CTRLR0_FRF_MASK (0x00000030)
1099 #define QM_SPI_CTRLR0_DFS_32_OFFSET (16)
1100 #define QM_SPI_CTRLR0_TMOD_OFFSET (8)
1101 #define QM_SPI_CTRLR0_SCPOL_SCPH_OFFSET (6)
1102 #define QM_SPI_CTRLR0_FRF_OFFSET (4)
1103 #define QM_SPI_CTRLR0_SLV_OE BIT(10)
1106 #define QM_SPI_SSIENR_SSIENR BIT(0)
1109 #define QM_SPI_SR_BUSY BIT(0)
1110 #define QM_SPI_SR_TFNF BIT(1)
1111 #define QM_SPI_SR_TFE BIT(2)
1112 #define QM_SPI_SR_RFNE BIT(3)
1113 #define QM_SPI_SR_RFF BIT(4)
1116 #define QM_SPI_IMR_MASK_ALL (0x00)
1117 #define QM_SPI_IMR_TXEIM BIT(0)
1118 #define QM_SPI_IMR_TXOIM BIT(1)
1119 #define QM_SPI_IMR_RXUIM BIT(2)
1120 #define QM_SPI_IMR_RXOIM BIT(3)
1121 #define QM_SPI_IMR_RXFIM BIT(4)
1124 #define QM_SPI_ISR_TXEIS BIT(0)
1125 #define QM_SPI_ISR_TXOIS BIT(1)
1126 #define QM_SPI_ISR_RXUIS BIT(2)
1127 #define QM_SPI_ISR_RXOIS BIT(3)
1128 #define QM_SPI_ISR_RXFIS BIT(4)
1131 #define QM_SPI_RISR_TXEIR BIT(0)
1132 #define QM_SPI_RISR_TXOIR BIT(1)
1133 #define QM_SPI_RISR_RXUIR BIT(2)
1134 #define QM_SPI_RISR_RXOIR BIT(3)
1135 #define QM_SPI_RISR_RXFIR BIT(4)
1138 #define QM_SPI_DMACR_RDMAE BIT(0)
1139 #define QM_SPI_DMACR_TDMAE BIT(1)
1153 QM_RW uint32_t rtc_ccvr;
1154 QM_RW uint32_t rtc_cmr;
1155 QM_RW uint32_t rtc_clr;
1156 QM_RW uint32_t rtc_ccr;
1157 QM_RW uint32_t rtc_stat;
1158 QM_RW uint32_t rtc_rstat;
1159 QM_RW uint32_t rtc_eoi;
1160 QM_RW uint32_t rtc_comp_version;
1164 #define qm_rtc_context_t uint8_t
1166 #define QM_RTC_CCR_INTERRUPT_ENABLE BIT(0)
1167 #define QM_RTC_CCR_INTERRUPT_MASK BIT(1)
1168 #define QM_RTC_CCR_ENABLE BIT(2)
1174 #define QM_RTC test_rtc
1179 #define QM_RTC_BASE (0xB0000400)
1182 #define QM_RTC qm_rtc
1193 typedef enum { QM_I2C_0 = 0, QM_I2C_1, QM_I2C_NUM }
qm_i2c_t;
1197 QM_RW uint32_t ic_con;
1198 QM_RW uint32_t ic_tar;
1199 QM_RW uint32_t ic_sar;
1200 QM_RW uint32_t ic_hs_maddr;
1201 QM_RW uint32_t ic_data_cmd;
1206 QM_RW uint32_t ic_fs_scl_hcnt;
1213 QM_RW uint32_t ic_intr_stat;
1214 QM_RW uint32_t ic_intr_mask;
1215 QM_RW uint32_t ic_raw_intr_stat;
1216 QM_RW uint32_t ic_rx_tl;
1217 QM_RW uint32_t ic_tx_tl;
1220 QM_RW uint32_t ic_clr_rx_under;
1221 QM_RW uint32_t ic_clr_rx_over;
1222 QM_RW uint32_t ic_clr_tx_over;
1223 QM_RW uint32_t ic_clr_rd_req;
1224 QM_RW uint32_t ic_clr_tx_abrt;
1225 QM_RW uint32_t ic_clr_rx_done;
1226 QM_RW uint32_t ic_clr_activity;
1227 QM_RW uint32_t ic_clr_stop_det;
1228 QM_RW uint32_t ic_clr_start_det;
1229 QM_RW uint32_t ic_clr_gen_call;
1230 QM_RW uint32_t ic_enable;
1231 QM_RW uint32_t ic_status;
1232 QM_RW uint32_t ic_txflr;
1233 QM_RW uint32_t ic_rxflr;
1234 QM_RW uint32_t ic_sda_hold;
1235 QM_RW uint32_t ic_tx_abrt_source;
1236 QM_RW uint32_t reserved;
1237 QM_RW uint32_t ic_dma_cr;
1239 QM_RW uint32_t ic_dma_tdlr;
1240 QM_RW uint32_t ic_dma_rdlr;
1241 QM_RW uint32_t ic_sda_setup;
1242 QM_RW uint32_t ic_ack_general_call;
1243 QM_RW uint32_t ic_enable_status;
1244 QM_RW uint32_t ic_fs_spklen;
1245 QM_RW uint32_t ic_hs_spklen;
1246 QM_RW uint32_t reserved1[19];
1247 QM_RW uint32_t ic_comp_param_1;
1248 QM_RW uint32_t ic_comp_version;
1249 QM_RW uint32_t ic_comp_type;
1250 QM_RW uint32_t padding[0xC0];
1278 #define QM_I2C test_i2c
1282 #define QM_I2C_0_BASE (0xB0002800)
1283 #define QM_I2C_1_BASE (0xB0002C00)
1287 #define QM_I2C qm_i2c
1290 #define QM_I2C_IC_ENABLE_CONTROLLER_EN BIT(0)
1291 #define QM_I2C_IC_ENABLE_CONTROLLER_ABORT BIT(1)
1292 #define QM_I2C_IC_ENABLE_STATUS_IC_EN BIT(0)
1293 #define QM_I2C_IC_CON_MASTER_MODE BIT(0)
1294 #define QM_I2C_IC_CON_SLAVE_DISABLE BIT(6)
1295 #define QM_I2C_IC_CON_10BITADDR_MASTER BIT(4)
1296 #define QM_I2C_IC_CON_10BITADDR_MASTER_OFFSET (4)
1297 #define QM_I2C_IC_CON_10BITADDR_SLAVE BIT(3)
1298 #define QM_I2C_IC_CON_10BITADDR_SLAVE_OFFSET (3)
1299 #define QM_I2C_IC_CON_SPEED_OFFSET (1)
1300 #define QM_I2C_IC_CON_SPEED_SS BIT(1)
1301 #define QM_I2C_IC_CON_SPEED_FS_FSP BIT(2)
1302 #define QM_I2C_IC_CON_SPEED_MASK (0x06)
1303 #define QM_I2C_IC_CON_RESTART_EN BIT(5)
1304 #define QM_I2C_IC_CON_STOP_DET_IFADDRESSED BIT(7)
1305 #define QM_I2C_IC_DATA_CMD_READ BIT(8)
1306 #define QM_I2C_IC_DATA_CMD_STOP_BIT_CTRL BIT(9)
1307 #define QM_I2C_IC_DATA_CMD_LSB_MASK (0x000000FF)
1308 #define QM_I2C_IC_RAW_INTR_STAT_RX_FULL BIT(2)
1309 #define QM_I2C_IC_RAW_INTR_STAT_TX_ABRT BIT(6)
1310 #define QM_I2C_IC_RAW_INTR_STAT_GEN_CALL BIT(11)
1311 #define QM_I2C_IC_RAW_INTR_STAT_RESTART_DETECTED BIT(12)
1312 #define QM_I2C_IC_TX_ABRT_SOURCE_NAK_MASK (0x1F)
1313 #define QM_I2C_IC_TX_ABRT_SOURCE_ARB_LOST BIT(12)
1314 #define QM_I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT BIT(9)
1315 #define QM_I2C_IC_TX_ABRT_SOURCE_ALL_MASK (0x1FFFF)
1316 #define QM_I2C_IC_STATUS_BUSY_MASK (0x00000060)
1317 #define QM_I2C_IC_STATUS_RFF BIT(4)
1318 #define QM_I2C_IC_STATUS_RFNE BIT(3)
1319 #define QM_I2C_IC_STATUS_TFE BIT(2)
1320 #define QM_I2C_IC_STATUS_TNF BIT(1)
1321 #define QM_I2C_IC_INTR_MASK_ALL (0x00)
1322 #define QM_I2C_IC_INTR_MASK_RX_UNDER BIT(0)
1323 #define QM_I2C_IC_INTR_MASK_RX_OVER BIT(1)
1324 #define QM_I2C_IC_INTR_MASK_RX_FULL BIT(2)
1325 #define QM_I2C_IC_INTR_MASK_TX_OVER BIT(3)
1326 #define QM_I2C_IC_INTR_MASK_TX_EMPTY BIT(4)
1327 #define QM_I2C_IC_INTR_MASK_RD_REQ BIT(5)
1328 #define QM_I2C_IC_INTR_MASK_TX_ABORT BIT(6)
1329 #define QM_I2C_IC_INTR_MASK_RX_DONE BIT(7)
1330 #define QM_I2C_IC_INTR_MASK_ACTIVITY BIT(8)
1331 #define QM_I2C_IC_INTR_MASK_STOP_DETECTED BIT(9)
1332 #define QM_I2C_IC_INTR_MASK_START_DETECTED BIT(10)
1333 #define QM_I2C_IC_INTR_MASK_GEN_CALL_DETECTED BIT(11)
1334 #define QM_I2C_IC_INTR_MASK_RESTART_DETECTED BIT(12)
1335 #define QM_I2C_IC_INTR_STAT_RX_UNDER BIT(0)
1336 #define QM_I2C_IC_INTR_STAT_RX_OVER BIT(1)
1337 #define QM_I2C_IC_INTR_STAT_RX_FULL BIT(2)
1338 #define QM_I2C_IC_INTR_STAT_TX_OVER BIT(3)
1339 #define QM_I2C_IC_INTR_STAT_TX_EMPTY BIT(4)
1340 #define QM_I2C_IC_INTR_STAT_RD_REQ BIT(5)
1341 #define QM_I2C_IC_INTR_STAT_TX_ABRT BIT(6)
1342 #define QM_I2C_IC_INTR_STAT_RX_DONE BIT(7)
1343 #define QM_I2C_IC_INTR_STAT_STOP_DETECTED BIT(9)
1344 #define QM_I2C_IC_INTR_STAT_START_DETECTED BIT(10)
1345 #define QM_I2C_IC_INTR_STAT_GEN_CALL_DETECTED BIT(11)
1346 #define QM_I2C_IC_LCNT_MAX (65525)
1347 #define QM_I2C_IC_LCNT_MIN (8)
1348 #define QM_I2C_IC_HCNT_MAX (65525)
1349 #define QM_I2C_IC_HCNT_MIN (6)
1350 #define QM_I2C_IC_TAR_MASK (0x3FF)
1352 #define QM_I2C_FIFO_SIZE (16)
1355 #define QM_I2C_IC_DMA_CR_RX_ENABLE BIT(0)
1356 #define QM_I2C_IC_DMA_CR_TX_ENABLE BIT(1)
1366 typedef enum { QM_GPIO_0 = 0, QM_AON_GPIO_0 = 1, QM_GPIO_NUM }
qm_gpio_t;
1370 QM_RW uint32_t gpio_swporta_dr;
1371 QM_RW uint32_t gpio_swporta_ddr;
1373 QM_RW uint32_t reserved[9];
1374 QM_RW uint32_t gpio_inten;
1375 QM_RW uint32_t gpio_intmask;
1376 QM_RW uint32_t gpio_inttype_level;
1377 QM_RW uint32_t gpio_int_polarity;
1378 QM_RW uint32_t gpio_intstatus;
1379 QM_RW uint32_t gpio_raw_intstatus;
1380 QM_RW uint32_t gpio_debounce;
1381 QM_RW uint32_t gpio_porta_eoi;
1382 QM_RW uint32_t gpio_ext_porta;
1383 QM_RW uint32_t reserved1[3];
1384 QM_RW uint32_t gpio_ls_sync;
1385 QM_RW uint32_t reserved2;
1386 QM_RW uint32_t gpio_int_bothedge;
1387 QM_RW uint32_t reserved3;
1388 QM_RW uint32_t gpio_config_reg2;
1389 QM_RW uint32_t gpio_config_reg1;
1412 #define QM_NUM_GPIO_PINS (32)
1413 #define QM_NUM_AON_GPIO_PINS (6)
1419 #define QM_GPIO test_gpio
1423 #define QM_GPIO_BASE (0xB0000C00)
1424 #define QM_AON_GPIO_BASE (QM_SCSS_CCU_BASE + 0xB00)
1428 #define QM_GPIO qm_gpio
1438 #define NUM_FLASH_CONTROLLERS (2)
1439 #define HAS_FLASH_WRITE_DISABLE (1)
1442 typedef enum { QM_FLASH_0 = 0, QM_FLASH_1, QM_FLASH_NUM }
qm_flash_t;
1446 QM_RW uint32_t tmg_ctrl;
1447 QM_RW uint32_t rom_wr_ctrl;
1448 QM_RW uint32_t rom_wr_data;
1449 QM_RW uint32_t flash_wr_ctrl;
1450 QM_RW uint32_t flash_wr_data;
1451 QM_RW uint32_t flash_stts;
1452 QM_RW uint32_t ctrl;
1453 QM_RW uint32_t fpr_rd_cfg[4];
1456 QM_RW uint32_t mpr_vsts;
1476 uint8_t test_flash_page[0x800];
1478 #define QM_FLASH test_flash
1480 #define QM_FLASH_REGION_SYS_1_BASE (test_flash_page)
1481 #define QM_FLASH_REGION_SYS_0_BASE (test_flash_page)
1482 #define QM_FLASH_REGION_OTP_0_BASE (test_flash_page)
1484 #define QM_FLASH_PAGE_MASK (0xCFF)
1485 #define QM_FLASH_MAX_ADDR (0xFFFFFFFF)
1490 #define QM_FLASH_REGION_SYS_1_BASE (0x40030000)
1491 #define QM_FLASH_REGION_SYS_0_BASE (0x40000000)
1492 #define QM_FLASH_REGION_OTP_0_BASE (0xFFFFE000)
1494 #define QM_FLASH_PAGE_MASK (0x3F800)
1495 #define QM_FLASH_MAX_ADDR (0x30000)
1498 #define QM_FLASH_BASE_0 (0xB0100000)
1499 #define QM_FLASH_BASE_1 (0xB0200000)
1503 #define QM_FLASH qm_flash
1507 #define QM_FLASH_REGION_DATA_BASE_OFFSET (0x00)
1508 #define QM_FLASH_MAX_WAIT_STATES (0xF)
1509 #define QM_FLASH_MAX_US_COUNT (0x3F)
1510 #define QM_FLASH_MAX_PAGE_NUM \
1511 (QM_FLASH_MAX_ADDR / (4 * QM_FLASH_PAGE_SIZE_DWORDS))
1512 #define QM_FLASH_CLK_SLOW BIT(14)
1513 #define QM_FLASH_LVE_MODE BIT(5)
1516 #define QM_FLASH_TMG_DEF_MASK (0xFFFFFC00)
1518 #define QM_FLASH_MICRO_SEC_COUNT_MASK (0x3F)
1520 #define QM_FLASH_WAIT_STATE_MASK (0x3C0)
1522 #define QM_FLASH_WAIT_STATE_OFFSET (6)
1524 #define QM_FLASH_WRITE_DISABLE_OFFSET (4)
1526 #define QM_FLASH_WRITE_DISABLE_VAL BIT(4)
1529 #define ER_REQ BIT(1)
1535 #define WR_DONE BIT(1)
1538 #define WR_ADDR_OFFSET (2)
1540 #define MASS_ERASE_INFO BIT(6)
1542 #define MASS_ERASE BIT(7)
1545 #define ROM_RD_DIS_U BIT(3)
1547 #define ROM_RD_DIS_L BIT(2)
1549 #define QM_FLASH_CTRL_PRE_FLUSH_MASK BIT(1)
1551 #define QM_FLASH_CTRL_PRE_EN_MASK BIT(0)
1553 #define QM_FLASH_ADDRESS_MASK (0x7FF)
1555 #define QM_FLASH_ADDR_INC (0x10)
1558 #define QM_FLASH_PAGE_SIZE_DWORDS (0x200)
1560 #define QM_FLASH_PAGE_SIZE_BYTES (0x800)
1562 #define QM_FLASH_PAGE_SIZE_BITS (11)
1564 #define QM_FLASH_STTS_ROM_PROG BIT(2)
1593 uint32_t fpr_rd_cfg[QM_FPR_NUM];
1597 #define QM_FPR_GRANULARITY (1024)
1617 QM_RW uint32_t mpr_cfg[4];
1618 QM_RW uint32_t mpr_vdata;
1619 QM_RW uint32_t mpr_vsts;
1634 #define QM_MPR_GRANULARITY (1024)
1639 #define QM_MPR ((qm_mpr_reg_t *)(&test_mpr))
1643 #define QM_MPR_BASE (0xB0400000)
1644 #define QM_MPR ((qm_mpr_reg_t *)QM_MPR_BASE)
1648 #define QM_MPR_UP_BOUND_OFFSET (10)
1649 #define QM_MPR_WR_EN_OFFSET (20)
1650 #define QM_MPR_WR_EN_MASK 0x700000
1651 #define QM_MPR_RD_EN_OFFSET (24)
1652 #define QM_MPR_RD_EN_MASK 0x7000000
1653 #define QM_MPR_EN_LOCK_OFFSET (30)
1654 #define QM_MPR_EN_LOCK_MASK 0xC0000000
1655 #define QM_MPR_VSTS_VALID BIT(31)
1658 #define QM_OSC0_PD BIT(2)
1660 #define QM_CCU_EXTERN_DIV_OFFSET (3)
1661 #define QM_CCU_EXT_CLK_DIV_EN BIT(2)
1701 #define CLK_EXTERN_DIV_DEF_MASK (0xFFFFFFE3)
1702 #define CLK_SYS_CLK_DIV_DEF_MASK (0xFFFFFC7F)
1703 #define CLK_RTC_DIV_DEF_MASK (0xFFFFFF83)
1704 #define CLK_GPIO_DB_DIV_DEF_MASK (0xFFFFFFE1)
1705 #define CLK_PERIPH_DIV_DEF_MASK (0xFFFFFFF9)
1755 QM_RW uint32_t sar_low;
1756 QM_RW uint32_t sar_high;
1757 QM_RW uint32_t dar_low;
1758 QM_RW uint32_t dar_high;
1759 QM_RW uint32_t llp_low;
1760 QM_RW uint32_t llp_high;
1761 QM_RW uint32_t ctrl_low;
1762 QM_RW uint32_t ctrl_high;
1763 QM_RW uint32_t src_stat_low;
1764 QM_RW uint32_t src_stat_high;
1765 QM_RW uint32_t dst_stat_low;
1766 QM_RW uint32_t dst_stat_high;
1767 QM_RW uint32_t src_stat_addr_low;
1768 QM_RW uint32_t src_stat_addr_high;
1769 QM_RW uint32_t dst_stat_addr_low;
1770 QM_RW uint32_t dst_stat_addr_high;
1771 QM_RW uint32_t cfg_low;
1772 QM_RW uint32_t cfg_high;
1773 QM_RW uint32_t src_sg_low;
1774 QM_RW uint32_t src_sg_high;
1775 QM_RW uint32_t dst_sg_low;
1776 QM_RW uint32_t dst_sg_high;
1780 #define QM_DMA_CTL_L_INT_EN_MASK BIT(0)
1781 #define QM_DMA_CTL_L_DST_TR_WIDTH_OFFSET (1)
1782 #define QM_DMA_CTL_L_DST_TR_WIDTH_MASK (0x7 << QM_DMA_CTL_L_DST_TR_WIDTH_OFFSET)
1783 #define QM_DMA_CTL_L_SRC_TR_WIDTH_OFFSET (4)
1784 #define QM_DMA_CTL_L_SRC_TR_WIDTH_MASK (0x7 << QM_DMA_CTL_L_SRC_TR_WIDTH_OFFSET)
1785 #define QM_DMA_CTL_L_DINC_OFFSET (7)
1786 #define QM_DMA_CTL_L_DINC_MASK (0x3 << QM_DMA_CTL_L_DINC_OFFSET)
1787 #define QM_DMA_CTL_L_SINC_OFFSET (9)
1788 #define QM_DMA_CTL_L_SINC_MASK (0x3 << QM_DMA_CTL_L_SINC_OFFSET)
1789 #define QM_DMA_CTL_L_DEST_MSIZE_OFFSET (11)
1790 #define QM_DMA_CTL_L_DEST_MSIZE_MASK (0x7 << QM_DMA_CTL_L_DEST_MSIZE_OFFSET)
1791 #define QM_DMA_CTL_L_SRC_MSIZE_OFFSET (14)
1792 #define QM_DMA_CTL_L_SRC_MSIZE_MASK (0x7 << QM_DMA_CTL_L_SRC_MSIZE_OFFSET)
1793 #define QM_DMA_CTL_L_TT_FC_OFFSET (20)
1794 #define QM_DMA_CTL_L_TT_FC_MASK (0x7 << QM_DMA_CTL_L_TT_FC_OFFSET)
1795 #define QM_DMA_CTL_L_LLP_DST_EN_MASK BIT(27)
1796 #define QM_DMA_CTL_L_LLP_SRC_EN_MASK BIT(28)
1797 #define QM_DMA_CTL_H_BLOCK_TS_OFFSET (0)
1798 #define QM_DMA_CTL_H_BLOCK_TS_MASK (0xfff << QM_DMA_CTL_H_BLOCK_TS_OFFSET)
1799 #define QM_DMA_CTL_H_BLOCK_TS_MAX 4095
1800 #define QM_DMA_CTL_H_BLOCK_TS_MIN 1
1803 #define QM_DMA_CFG_L_CH_SUSP_MASK BIT(8)
1804 #define QM_DMA_CFG_L_FIFO_EMPTY_MASK BIT(9)
1805 #define QM_DMA_CFG_L_HS_SEL_DST_OFFSET 10
1806 #define QM_DMA_CFG_L_HS_SEL_DST_MASK BIT(QM_DMA_CFG_L_HS_SEL_DST_OFFSET)
1807 #define QM_DMA_CFG_L_HS_SEL_SRC_OFFSET 11
1808 #define QM_DMA_CFG_L_HS_SEL_SRC_MASK BIT(QM_DMA_CFG_L_HS_SEL_SRC_OFFSET)
1809 #define QM_DMA_CFG_L_DST_HS_POL_OFFSET 18
1810 #define QM_DMA_CFG_L_DST_HS_POL_MASK BIT(QM_DMA_CFG_L_DST_HS_POL_OFFSET)
1811 #define QM_DMA_CFG_L_SRC_HS_POL_OFFSET 19
1812 #define QM_DMA_CFG_L_SRC_HS_POL_MASK BIT(QM_DMA_CFG_L_SRC_HS_POL_OFFSET)
1813 #define QM_DMA_CFG_L_RELOAD_SRC_MASK BIT(30)
1814 #define QM_DMA_CFG_L_RELOAD_DST_MASK BIT(31)
1815 #define QM_DMA_CFG_H_DS_UPD_EN_OFFSET (5)
1816 #define QM_DMA_CFG_H_DS_UPD_EN_MASK BIT(QM_DMA_CFG_H_DS_UPD_EN_OFFSET)
1817 #define QM_DMA_CFG_H_SS_UPD_EN_OFFSET (6)
1818 #define QM_DMA_CFG_H_SS_UPD_EN_MASK BIT(QM_DMA_CFG_H_SS_UPD_EN_OFFSET)
1819 #define QM_DMA_CFG_H_SRC_PER_OFFSET (7)
1820 #define QM_DMA_CFG_H_SRC_PER_MASK (0xf << QM_DMA_CFG_H_SRC_PER_OFFSET)
1821 #define QM_DMA_CFG_H_DEST_PER_OFFSET (11)
1822 #define QM_DMA_CFG_H_DEST_PER_MASK (0xf << QM_DMA_CFG_H_DEST_PER_OFFSET)
1824 #define QM_DMA_ENABLE_CLOCK(dma) \
1825 (QM_SCSS_CCU->ccu_mlayer_ahb_ctl |= QM_CCU_DMA_CLK_EN)
1829 QM_RW uint32_t raw_tfr_low;
1830 QM_RW uint32_t raw_tfr_high;
1831 QM_RW uint32_t raw_block_low;
1832 QM_RW uint32_t raw_block_high;
1833 QM_RW uint32_t raw_src_trans_low;
1834 QM_RW uint32_t raw_src_trans_high;
1835 QM_RW uint32_t raw_dst_trans_low;
1836 QM_RW uint32_t raw_dst_trans_high;
1837 QM_RW uint32_t raw_err_low;
1838 QM_RW uint32_t raw_err_high;
1839 QM_RW uint32_t status_tfr_low;
1840 QM_RW uint32_t status_tfr_high;
1841 QM_RW uint32_t status_block_low;
1842 QM_RW uint32_t status_block_high;
1843 QM_RW uint32_t status_src_trans_low;
1844 QM_RW uint32_t status_src_trans_high;
1845 QM_RW uint32_t status_dst_trans_low;
1846 QM_RW uint32_t status_dst_trans_high;
1847 QM_RW uint32_t status_err_low;
1848 QM_RW uint32_t status_err_high;
1849 QM_RW uint32_t mask_tfr_low;
1850 QM_RW uint32_t mask_tfr_high;
1851 QM_RW uint32_t mask_block_low;
1852 QM_RW uint32_t mask_block_high;
1853 QM_RW uint32_t mask_src_trans_low;
1854 QM_RW uint32_t mask_src_trans_high;
1855 QM_RW uint32_t mask_dst_trans_low;
1856 QM_RW uint32_t mask_dst_trans_high;
1857 QM_RW uint32_t mask_err_low;
1858 QM_RW uint32_t mask_err_high;
1859 QM_RW uint32_t clear_tfr_low;
1860 QM_RW uint32_t clear_tfr_high;
1861 QM_RW uint32_t clear_block_low;
1862 QM_RW uint32_t clear_block_high;
1863 QM_RW uint32_t clear_src_trans_low;
1864 QM_RW uint32_t clear_src_trans_high;
1865 QM_RW uint32_t clear_dst_trans_low;
1866 QM_RW uint32_t clear_dst_trans_high;
1867 QM_RW uint32_t clear_err_low;
1868 QM_RW uint32_t clear_err_high;
1869 QM_RW uint32_t status_int_low;
1870 QM_RW uint32_t status_int_high;
1874 #define QM_DMA_INT_STATUS_TFR BIT(0)
1875 #define QM_DMA_INT_STATUS_BLOCK BIT(1)
1876 #define QM_DMA_INT_STATUS_ERR BIT(4)
1880 QM_RW uint32_t cfg_low;
1881 QM_RW uint32_t cfg_high;
1882 QM_RW uint32_t chan_en_low;
1883 QM_RW uint32_t chan_en_high;
1884 QM_RW uint32_t id_low;
1885 QM_RW uint32_t id_high;
1886 QM_RW uint32_t test_low;
1887 QM_RW uint32_t test_high;
1888 QM_RW uint32_t reserved[4];
1892 #define QM_DMA_MISC_CHAN_EN_WE_OFFSET (8)
1895 #define QM_DMA_MISC_CFG_DMA_EN BIT(0)
1900 QM_RW uint32_t reserved[12];
1924 #define QM_DMA test_dma
1926 #define QM_DMA_BASE (0xB0700000)
1928 #define QM_DMA qm_dma
1938 #define QM_USB_EP_DIR_IN_MASK (0x80)
1939 #define QM_USB_IN_EP_NUM (6)
1940 #define QM_USB_OUT_EP_NUM (4)
1941 #define QM_USB_MAX_PACKET_SIZE (64)
1953 QM_USB_OUT_EP_0 = 6,
1954 QM_USB_OUT_EP_1 = 7,
1955 QM_USB_OUT_EP_2 = 8,
1963 QM_RW uint32_t diepctl;
1964 QM_R uint32_t reserved;
1965 QM_RW uint32_t diepint;
1966 QM_R uint32_t reserved1;
1967 QM_RW uint32_t dieptsiz;
1968 QM_RW uint32_t diepdma;
1969 QM_RW uint32_t dtxfsts;
1970 QM_R uint32_t reserved2;
1975 QM_RW uint32_t doepctl;
1976 QM_R uint32_t reserved;
1977 QM_RW uint32_t doepint;
1978 QM_R uint32_t reserved1;
1979 QM_RW uint32_t doeptsiz;
1980 QM_RW uint32_t doepdma;
1981 QM_R uint32_t reserved2[2];
1999 QM_R uint32_t reserved[5];
2006 QM_R uint32_t reserved1[43];
2007 QM_RW uint32_t dieptxf1;
2008 QM_RW uint32_t dieptxf2;
2009 QM_RW uint32_t dieptxf3;
2010 QM_RW uint32_t dieptxf4;
2011 QM_RW uint32_t dieptxf5;
2012 QM_R uint32_t reserved2[442];
2016 QM_R uint32_t reserved3;
2021 QM_R uint32_t reserved4[2];
2026 QM_R uint32_t reserved5[50];
2028 QM_R uint32_t reserved6[80];
2034 #define QM_USB ((qm_usb_reg_t *)(&test_usb))
2036 #define QM_USB_0_BASE (0xB0500000)
2038 #define QM_USB ((qm_usb_reg_t *)QM_USB_0_BASE)
2042 #define QM_USB_PLL_PDLD BIT(0)
2044 #define QM_USB_PLL_LOCK BIT(14)
2046 #define QM_USB_PLL_CFG0_DEFAULT (0x00001904)
2050 uint32_t test_usb_pll;
2051 #define QM_USB_PLL_CFG0 (test_usb_pll)
2053 #define QM_USB_PLL_CFG0 (REG_VAL(0xB0800014))
2057 #define QM_CCU_USB_CLK_EN BIT(1)
2079 uint32_t test_rom_version;
2080 #define ROM_VERSION_ADDRESS &test_rom_version;
2082 #define ROM_VERSION_ADDRESS \
2083 (BL_DATA_FLASH_REGION_BASE + \
2084 (BL_DATA_SECTION_BASE_PAGE * QM_FLASH_PAGE_SIZE_BYTES) + \
2085 sizeof(qm_flash_data_trim_t))
uint32_t dlh
Divisor Latch High.
I2C Master 1 Clock Gate Enable.
uint32_t baudr
Baud Rate Select.
DMA channel id for channel 5.
uint32_t cfg_high
Channel Configuration Upper.
QM_RW apic_reg_pad_t lvtpmcr
Perfmon counter vector.
DMA interrupt register map.
QM_RW apic_reg_pad_t esr
Error status.
uint32_t gpio_swporta_ddr
Port A Data Direction.
uint32_t gpio_inttype_level
Interrupt Type.
QM_RW apic_reg_pad_t ppr
Processor priority.
uint32_t ctrl
Control Register.
QM_R uint32_t daint
Device Interrupt Register.
uint32_t mcr
Modem Control.
QM_RW uint32_t pm1c
Power management 1 control.
QM_RW uint32_t plat3p3_vr
Platform 3p3 voltage regulator.
uint32_t timer_icr
Initial Count Register.
GPIO Debounce Clock Enable.
uint32_t llp_low
Channel Linked List Pointer.
QM_RW apic_reg_pad_t lvtlint0
Local interrupt 0 vector.
QM_RW apic_reg_pad_t apr
Arbitration priority.
DMA channel id for channel 2.
uint32_t gpio_ls_sync
Synchronization Level.
uint32_t tx_tl
Receive FIFO threshold register.
uint32_t fs_scl_hcnt
Fast Speed Clock SCL High Count.
UART context to be saved between sleep/resume.
uint32_t tmg_ctrl
Flash Timing Control Register.
uint32_t gpio_intmask
Interrupt Mask.
QM_RW uint32_t gotgint
OTG Interrupt.
I2C Master 1 Clock Enable.
qm_flash_t
Number of Flash controllers.
uint32_t con
Control Register.
QM_RW uint32_t ch_ctrl
Channel Control Word.
uint32_t ser
Slave Enable Register.
QM_RW uint32_t gdfifocfg
Global DFIFO Configuration.
Number of Memory Protection Regions.
QM_RW apic_reg_pad_t timer_icr
Timer initial count.
QM_RW uint32_t p_lvl2
Processor level 2.
QM_RW uint32_t mbox_chall_sts
All channel status.
QM_RW apic_reg_pad_t timer_dcr
Timer divide configuration.
QM_RW uint32_t doepmsk
OUT EP Common Interrupt Mask.
Quark D2000 peripherals Enable.
DMA channel id for channel 1.
QM_RW uint32_t usb_pll_cfg0
USB Phase lock look configuration.
QM_RW apic_reg_pad_t lvtlint1
Local interrupt 1 vector.
QM_RW uint32_t host_vr
Host Voltage Regulator.
qm_uart_t
Number of UART controllers.
Memory Protection Region 0.
Memory Protection Region 3.
QM_RW uint32_t gintmsk
Interrupt Mask.
uint32_t htx
Halt Transmission.
uint32_t fs_scl_lcnt
Fast Speed I2C Clock SCL Low Count.
QM_RW apic_reg_pad_t lvtts
Thermal sensor vector.
uint32_t gpio_int_polarity
Interrupt Polarity.
Peripheral Clock Gate Enable.
uint32_t cfg_low
Channel Configuration Lower.
QM_RW apic_reg_pad_t lvtcmci
Corrected Machine Check vector.
uint32_t ctrl_low
Channel Control Lower.
QM_RW uint32_t ccu_ss_periph_clk_gate_ctl
Sensor Subsystem peripheral clock gate control.
qm_spi_reg_t * qm_spi_controllers[QM_SPI_NUM]
Extern qm_spi_reg_t* array declared at qm_soc_regs.h .
PWM / Timer register map.
SPI Master 0 Clock Enable.
SPI Master 1 Clock Gate Enable.
DMA miscellaneous register map.
Information register map.
QM_RW apic_reg_pad_t version
LAPIC version.
QM_R uint32_t ghwcfg4
HW config 4.
System Core register map.
uint32_t loadcount
Load Count 1.
QM_RW uint32_t dthrctl
Device Threshold Ctrl.
QM_RW uint32_t dvbusdis
VBUS discharge time register.
QM_RW uint32_t ss_sts
Sensor Subsystem status.
QM_R uint32_t gnptxfsiz
Non-periodic Transmit FIFO Size.
Always-on Counter Controller register map.
QM_RW uint32_t gahbcfg
AHB Configuration.
uint32_t timer_dcr
Divide Configuration Register.
uint32_t gpio_int_bothedge
Interrupt both edge type.
General Purpose register map.
QM_RW uint32_t dctl
Device control.
QM_RW uint32_t gintsts
Interrupt Status.
qm_spi_t
Number of SPI controllers.
DMA channel id for channel 6.
QM_RW uint32_t pmnetcs
Power Management Network (PMNet) Control and Status.
qm_rtc_t
Number of RTC controllers.
QM_RW uint32_t gpio_swporta_ctl
Port A Data Source.
QM_RW apic_reg_pad_t tpr
Task priority.
QM_R uint32_t ghwcfg1
HW config - Endpoint direction.
QM_RW apic_reg_pad_t id
LAPIC ID.
QM_R uint32_t ghwcfg2
HW config 2.
QM_RW uint32_t dsts
Device Status.
QM_RW uint32_t mem_ctrl
Memory control.
QM_RW uint32_t ch_sts
Channel status.
qm_gpio_reg_t * qm_gpio[QM_GPIO_NUM]
GPIO register block.
QM_R uint32_t grxstsr
Receive Status Read/Pop.
uint32_t gpio_inten
Interrupt Enable.
uint32_t ss_scl_lcnt
Standard Speed Clock SCL Low Count.
uint32_t ss_scl_hcnt
Standard Speed Clock SCL High Count.
QM_RW apic_reg_pad_t lvterr
Error vector.
APIC register block type.
Number of DMA controllers.
DMA channel id for channel 0.
I2C Master 0 Clock Gate Enable.
DMA channel id for channel 3.
Mailbox register structure.
uint32_t dll
Divisor Latch Low.
SPI Slave Clock Gate Enable.
uint32_t ic_intr_mask
I2C Interrupt Mask.
I2C Master 0 Clock Enable.
DMA channel id for channel 7.
QM_RW apic_reg_pad_t timer_ccr
Timer current count.
Memory Protection Region 2.
uint32_t gpio_swporta_dr
Port A Data.
Memory Control register map.
uint32_t loadcount2
Load Count 2.
SPI Master 0 Clock Gate Enable.
qm_gpio_t
Number of GPIO controllers.
qm_fpr_id_t
FPR register map.
DMA channel register map.
qm_i2c_t
Number of I2C controllers.
uint32_t gpio_debounce
Debounce Enable.
QM_RW uint32_t dcfg
Device config.
QM_R uint32_t grxfsiz
Receive FIFO Size.
qm_i2c_reg_t * qm_i2c[QM_I2C_NUM]
I2C register block.
QM_RW uint32_t rev
Revision Register.
I2C context to be saved between sleep/resume.
Memory Protection Region register map.
QM_RW uint32_t diepempmsk
IN EP FIFO Empty Intr Mask.
DMA channel id for channel 4.
QM_R uint32_t gsnpsid
Synopsys ID.
qm_pwm_t
Number of PWM / Timer controllers.
uint32_t ctrlr0
Control Register 0.
Sensor Subsystem register map.
qm_usb_t
Number of USB controllers.
QM_RW uint32_t usb_phy_cfg0
USB Configuration.
uint32_t misc_cfg_low
DMA Configuration.
QM_RW uint32_t gotgctl
OTG Control.
QM_RW uint32_t diepmsk
IN EP Common Interrupt Mask.
QM_RW uint32_t gusbcfg
USB Configuration.
QM_RW uint32_t dvbuspulse
Device VBUS discharge time.
uint32_t fs_spklen
SS and FS Spike Suppression Limit.
Memory Protection Region 1.
qm_dma_channel_id_t
DMA channel IDs.
QM_RW uint32_t plat1p8_vr
Platform 1p8 voltage regulator.
clk_periph_t
Peripheral clock register map.
uint32_t gpio_swporta_ctl
Port A Data Source.
uint32_t lvttimer
Timer Entry in Local Vector Table.
Power Management register map.
QM_RW apic_reg_pad_t ldr
Logical destination.
qm_dma_handshake_interface_t
DMA hardware handshake interfaces.
QM_RW uint32_t daintmsk
Device Interrupt Mask Register.
QM_RW apic_reg_pad_t dfr
Destination format.
QM_RW uint32_t ss_cfg
Sensor Subsystem Configuration.
PWM / Timer channel register map.
uint32_t lcr
Line Control.
qm_wdt_t
Number of WDT controllers.
QM_RW apic_reg_pad_t rrd
Remote read.
Watchdog timer register map.
uint32_t sar
Slave Address.
uint32_t dlf
Divisor Latch Fraction.
QM_RW uint32_t vr_lock
Voltage regulator lock.
Peripheral Registers register map.
QM_RW apic_reg_pad_t svr
Spurious vector.
QM_RW uint32_t slp_cfg
Sleeping Configuration.
SPI Master 1 Clock Enable.
QM_R uint32_t grxstsp
Receive Status Read/Pop.
uint32_t ier
Interrupt Enable Register.
QM_RW uint32_t id
Identification Register.
QM_R uint32_t ghwcfg3
HW config 3.
QM_RW uint32_t grstctl
Reset Register.
qm_aonc_t
Number of Always-on counter controllers.
QM_RW apic_reg_pad_t lvttimer
Timer vector.
QM_RW apic_reg_pad_t eoi
End of interrupt.
GPIO Interrupt Clock Enable.
uint32_t controlreg
Control Register.