Intel® Quark™ Microcontroller Software Interface
1.4.0
Intel® Quark™ Microcontroller BSP
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I2C register map. More...
#include <qm_soc_regs.h>
Data Fields | |
QM_RW uint32_t | ic_con |
Control Register. More... | |
QM_RW uint32_t | ic_tar |
Master Target Address. More... | |
QM_RW uint32_t | ic_sar |
Slave Address. More... | |
QM_RW uint32_t | ic_hs_maddr |
High Speed Master ID. More... | |
QM_RW uint32_t | ic_data_cmd |
Data Buffer and Command. More... | |
QM_RW uint32_t | ic_ss_scl_hcnt |
Standard Speed Clock SCL High Count. More... | |
QM_RW uint32_t | ic_ss_scl_lcnt |
Standard Speed Clock SCL Low Count. More... | |
QM_RW uint32_t | ic_fs_scl_hcnt |
Fast Speed Clock SCL High Count. More... | |
QM_RW uint32_t | ic_fs_scl_lcnt |
Fast Speed I2C Clock SCL Low Count. More... | |
QM_RW uint32_t | ic_hs_scl_hcnt |
High Speed I2C Clock SCL High Count. More... | |
QM_RW uint32_t | ic_hs_scl_lcnt |
High Speed I2C Clock SCL Low Count. More... | |
QM_RW uint32_t | ic_intr_stat |
Interrupt Status. More... | |
QM_RW uint32_t | ic_intr_mask |
Interrupt Mask. More... | |
QM_RW uint32_t | ic_raw_intr_stat |
Raw Interrupt Status. More... | |
QM_RW uint32_t | ic_rx_tl |
Receive FIFO Threshold Level. More... | |
QM_RW uint32_t | ic_tx_tl |
Transmit FIFO Threshold Level. More... | |
QM_RW uint32_t | ic_clr_intr |
Clear Combined and Individual Interrupt. More... | |
QM_RW uint32_t | ic_clr_rx_under |
Clear RX_UNDER Interrupt. More... | |
QM_RW uint32_t | ic_clr_rx_over |
Clear RX_OVER Interrupt. More... | |
QM_RW uint32_t | ic_clr_tx_over |
Clear TX_OVER Interrupt. More... | |
QM_RW uint32_t | ic_clr_rd_req |
Clear RD_REQ Interrupt. More... | |
QM_RW uint32_t | ic_clr_tx_abrt |
Clear TX_ABRT Interrupt. More... | |
QM_RW uint32_t | ic_clr_rx_done |
Clear RX_DONE Interrupt. More... | |
QM_RW uint32_t | ic_clr_activity |
Clear ACTIVITY Interrupt. More... | |
QM_RW uint32_t | ic_clr_stop_det |
Clear STOP_DET Interrupt. More... | |
QM_RW uint32_t | ic_clr_start_det |
Clear START_DET Interrupt. More... | |
QM_RW uint32_t | ic_clr_gen_call |
Clear GEN_CALL Interrupt. More... | |
QM_RW uint32_t | ic_enable |
Enable. More... | |
QM_RW uint32_t | ic_status |
Status. More... | |
QM_RW uint32_t | ic_txflr |
Transmit FIFO Level. More... | |
QM_RW uint32_t | ic_rxflr |
Receive FIFO Level. More... | |
QM_RW uint32_t | ic_sda_hold |
SDA Hold. More... | |
QM_RW uint32_t | ic_tx_abrt_source |
Transmit Abort Source. More... | |
QM_RW uint32_t | ic_dma_cr |
SDA Setup. More... | |
QM_RW uint32_t | ic_dma_tdlr |
DMA Transmit Data Level Register. More... | |
QM_RW uint32_t | ic_dma_rdlr |
I2C Receive Data Level Register. More... | |
QM_RW uint32_t | ic_sda_setup |
SDA Setup. More... | |
QM_RW uint32_t | ic_ack_general_call |
General Call Ack. More... | |
QM_RW uint32_t | ic_enable_status |
Enable Status. More... | |
QM_RW uint32_t | ic_fs_spklen |
SS and FS Spike Suppression Limit. More... | |
QM_RW uint32_t | ic_hs_spklen |
HS spike suppression limit. More... | |
QM_RW uint32_t | ic_clr_restart_det |
clear the RESTART_DET interrupt. More... | |
QM_RW uint32_t | ic_comp_param_1 |
Configuration Parameters. More... | |
QM_RW uint32_t | ic_comp_version |
Component Version. More... | |
QM_RW uint32_t | ic_comp_type |
Component Type. More... | |
I2C register map.
Definition at line 864 of file qm_soc_regs.h.
QM_RW uint32_t qm_i2c_reg_t::ic_ack_general_call |
General Call Ack.
Definition at line 909 of file qm_soc_regs.h.
QM_RW uint32_t qm_i2c_reg_t::ic_clr_activity |
Clear ACTIVITY Interrupt.
Definition at line 894 of file qm_soc_regs.h.
QM_RW uint32_t qm_i2c_reg_t::ic_clr_gen_call |
Clear GEN_CALL Interrupt.
Definition at line 897 of file qm_soc_regs.h.
QM_RW uint32_t qm_i2c_reg_t::ic_clr_intr |
Clear Combined and Individual Interrupt.
Definition at line 887 of file qm_soc_regs.h.
QM_RW uint32_t qm_i2c_reg_t::ic_clr_rd_req |
Clear RD_REQ Interrupt.
Definition at line 891 of file qm_soc_regs.h.
QM_RW uint32_t qm_i2c_reg_t::ic_clr_restart_det |
clear the RESTART_DET interrupt.
Definition at line 914 of file qm_soc_regs.h.
QM_RW uint32_t qm_i2c_reg_t::ic_clr_rx_done |
Clear RX_DONE Interrupt.
Definition at line 893 of file qm_soc_regs.h.
QM_RW uint32_t qm_i2c_reg_t::ic_clr_rx_over |
Clear RX_OVER Interrupt.
Definition at line 889 of file qm_soc_regs.h.
QM_RW uint32_t qm_i2c_reg_t::ic_clr_rx_under |
Clear RX_UNDER Interrupt.
Definition at line 888 of file qm_soc_regs.h.
QM_RW uint32_t qm_i2c_reg_t::ic_clr_start_det |
Clear START_DET Interrupt.
Definition at line 896 of file qm_soc_regs.h.
QM_RW uint32_t qm_i2c_reg_t::ic_clr_stop_det |
Clear STOP_DET Interrupt.
Definition at line 895 of file qm_soc_regs.h.
QM_RW uint32_t qm_i2c_reg_t::ic_clr_tx_abrt |
Clear TX_ABRT Interrupt.
Definition at line 892 of file qm_soc_regs.h.
Referenced by qm_i2c_master_read(), and qm_i2c_master_write().
QM_RW uint32_t qm_i2c_reg_t::ic_clr_tx_over |
Clear TX_OVER Interrupt.
Definition at line 890 of file qm_soc_regs.h.
QM_RW uint32_t qm_i2c_reg_t::ic_comp_param_1 |
Configuration Parameters.
Definition at line 916 of file qm_soc_regs.h.
QM_RW uint32_t qm_i2c_reg_t::ic_comp_type |
Component Type.
Definition at line 918 of file qm_soc_regs.h.
QM_RW uint32_t qm_i2c_reg_t::ic_comp_version |
Component Version.
Definition at line 917 of file qm_soc_regs.h.
QM_RW uint32_t qm_i2c_reg_t::ic_con |
Control Register.
Definition at line 865 of file qm_soc_regs.h.
Referenced by qm_i2c_restore_context(), qm_i2c_save_context(), qm_i2c_set_config(), and qm_i2c_set_speed().
QM_RW uint32_t qm_i2c_reg_t::ic_data_cmd |
Data Buffer and Command.
Definition at line 869 of file qm_soc_regs.h.
Referenced by qm_i2c_master_read(), and qm_i2c_master_write().
QM_RW uint32_t qm_i2c_reg_t::ic_dma_cr |
SDA Setup.
DMA Control Register for Tx and Rx Handshaking Interface.
Definition at line 905 of file qm_soc_regs.h.
QM_RW uint32_t qm_i2c_reg_t::ic_dma_rdlr |
I2C Receive Data Level Register.
Definition at line 907 of file qm_soc_regs.h.
QM_RW uint32_t qm_i2c_reg_t::ic_dma_tdlr |
DMA Transmit Data Level Register.
Definition at line 906 of file qm_soc_regs.h.
QM_RW uint32_t qm_i2c_reg_t::ic_enable |
Enable.
Definition at line 898 of file qm_soc_regs.h.
Referenced by qm_i2c_restore_context(), and qm_i2c_save_context().
QM_RW uint32_t qm_i2c_reg_t::ic_enable_status |
Enable Status.
Definition at line 910 of file qm_soc_regs.h.
QM_RW uint32_t qm_i2c_reg_t::ic_fs_scl_hcnt |
Fast Speed Clock SCL High Count.
Definition at line 874 of file qm_soc_regs.h.
Referenced by qm_i2c_restore_context(), qm_i2c_save_context(), qm_i2c_set_config(), and qm_i2c_set_speed().
QM_RW uint32_t qm_i2c_reg_t::ic_fs_scl_lcnt |
Fast Speed I2C Clock SCL Low Count.
Definition at line 876 of file qm_soc_regs.h.
Referenced by qm_i2c_restore_context(), qm_i2c_save_context(), qm_i2c_set_config(), and qm_i2c_set_speed().
QM_RW uint32_t qm_i2c_reg_t::ic_fs_spklen |
SS and FS Spike Suppression Limit.
Definition at line 911 of file qm_soc_regs.h.
Referenced by qm_i2c_restore_context(), qm_i2c_save_context(), qm_i2c_set_config(), and qm_i2c_set_speed().
QM_RW uint32_t qm_i2c_reg_t::ic_hs_maddr |
High Speed Master ID.
Definition at line 868 of file qm_soc_regs.h.
QM_RW uint32_t qm_i2c_reg_t::ic_hs_scl_hcnt |
High Speed I2C Clock SCL High Count.
Definition at line 878 of file qm_soc_regs.h.
QM_RW uint32_t qm_i2c_reg_t::ic_hs_scl_lcnt |
High Speed I2C Clock SCL Low Count.
Definition at line 880 of file qm_soc_regs.h.
QM_RW uint32_t qm_i2c_reg_t::ic_hs_spklen |
HS spike suppression limit.
Definition at line 912 of file qm_soc_regs.h.
QM_RW uint32_t qm_i2c_reg_t::ic_intr_mask |
Interrupt Mask.
Definition at line 882 of file qm_soc_regs.h.
Referenced by qm_i2c_master_irq_transfer(), qm_i2c_restore_context(), qm_i2c_save_context(), qm_i2c_set_config(), and qm_i2c_slave_irq_transfer().
QM_RW uint32_t qm_i2c_reg_t::ic_intr_stat |
Interrupt Status.
Definition at line 881 of file qm_soc_regs.h.
QM_RW uint32_t qm_i2c_reg_t::ic_raw_intr_stat |
Raw Interrupt Status.
Definition at line 883 of file qm_soc_regs.h.
Referenced by qm_i2c_master_read().
QM_RW uint32_t qm_i2c_reg_t::ic_rx_tl |
Receive FIFO Threshold Level.
Definition at line 884 of file qm_soc_regs.h.
Referenced by qm_i2c_master_irq_transfer(), qm_i2c_restore_context(), qm_i2c_save_context(), and qm_i2c_slave_irq_transfer().
QM_RW uint32_t qm_i2c_reg_t::ic_rxflr |
Receive FIFO Level.
Definition at line 901 of file qm_soc_regs.h.
QM_RW uint32_t qm_i2c_reg_t::ic_sar |
Slave Address.
Definition at line 867 of file qm_soc_regs.h.
Referenced by qm_i2c_restore_context(), qm_i2c_save_context(), and qm_i2c_set_config().
QM_RW uint32_t qm_i2c_reg_t::ic_sda_hold |
SDA Hold.
Definition at line 902 of file qm_soc_regs.h.
QM_RW uint32_t qm_i2c_reg_t::ic_sda_setup |
SDA Setup.
Definition at line 908 of file qm_soc_regs.h.
QM_RW uint32_t qm_i2c_reg_t::ic_ss_scl_hcnt |
Standard Speed Clock SCL High Count.
Definition at line 871 of file qm_soc_regs.h.
Referenced by qm_i2c_restore_context(), qm_i2c_save_context(), qm_i2c_set_config(), and qm_i2c_set_speed().
QM_RW uint32_t qm_i2c_reg_t::ic_ss_scl_lcnt |
Standard Speed Clock SCL Low Count.
Definition at line 873 of file qm_soc_regs.h.
Referenced by qm_i2c_restore_context(), qm_i2c_save_context(), qm_i2c_set_config(), and qm_i2c_set_speed().
QM_RW uint32_t qm_i2c_reg_t::ic_status |
Status.
Definition at line 899 of file qm_soc_regs.h.
Referenced by qm_i2c_get_status(), qm_i2c_master_read(), and qm_i2c_master_write().
QM_RW uint32_t qm_i2c_reg_t::ic_tar |
Master Target Address.
Definition at line 866 of file qm_soc_regs.h.
Referenced by qm_i2c_master_irq_transfer(), qm_i2c_master_read(), and qm_i2c_master_write().
QM_RW uint32_t qm_i2c_reg_t::ic_tx_abrt_source |
Transmit Abort Source.
Definition at line 903 of file qm_soc_regs.h.
Referenced by qm_i2c_get_status(), qm_i2c_master_read(), and qm_i2c_master_write().
QM_RW uint32_t qm_i2c_reg_t::ic_tx_tl |
Transmit FIFO Threshold Level.
Definition at line 885 of file qm_soc_regs.h.
Referenced by qm_i2c_master_irq_transfer(), qm_i2c_restore_context(), qm_i2c_save_context(), and qm_i2c_slave_irq_transfer().
QM_RW uint32_t qm_i2c_reg_t::ic_txflr |
Transmit FIFO Level.
Definition at line 900 of file qm_soc_regs.h.