Intel® Quark™ Microcontroller Software Interface
1.4.0
Intel® Quark™ Microcontroller BSP
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Interrupt Service Routines. More...
Functions | |
QM_ISR_DECLARE (qm_adc_0_cal_isr) | |
ISR for ADC 0 convert and calibration interrupt. More... | |
QM_ISR_DECLARE (qm_adc_0_pwr_isr) | |
ISR for ADC 0 change mode interrupt. More... | |
QM_ISR_DECLARE (qm_aonpt_0_isr) | |
ISR for Always-on Periodic Timer 0 interrupt. More... | |
QM_ISR_DECLARE (qm_comparator_0_isr) | |
ISR for Analog Comparator 0 interrupt. More... | |
QM_ISR_DECLARE (qm_dma_0_error_isr) | |
ISR for DMA error interrupt. More... | |
QM_ISR_DECLARE (qm_dma_0_isr_0) | |
ISR for DMA channel 0 interrupt. More... | |
QM_ISR_DECLARE (qm_dma_0_isr_1) | |
ISR for DMA channel 1 interrupt. More... | |
QM_ISR_DECLARE (qm_dma_0_isr_2) | |
ISR for DMA channel 2 interrupt. More... | |
QM_ISR_DECLARE (qm_dma_0_isr_3) | |
ISR for DMA channel 3 interrupt. More... | |
QM_ISR_DECLARE (qm_dma_0_isr_4) | |
ISR for DMA channel 4 interrupt. More... | |
QM_ISR_DECLARE (qm_dma_0_isr_5) | |
ISR for DMA channel 5 interrupt. More... | |
QM_ISR_DECLARE (qm_dma_0_isr_6) | |
ISR for DMA channel 6 interrupt. More... | |
QM_ISR_DECLARE (qm_dma_0_isr_7) | |
ISR for DMA 0 channel 7 interrupt. More... | |
QM_ISR_DECLARE (qm_flash_mpr_0_isr) | |
ISR for FPR 0 interrupt. More... | |
QM_ISR_DECLARE (qm_flash_mpr_1_isr) | |
ISR for FPR 1 interrupt. More... | |
QM_ISR_DECLARE (qm_gpio_0_isr) | |
ISR for GPIO 0 interrupt. More... | |
QM_ISR_DECLARE (qm_aon_gpio_0_isr) | |
ISR for AON GPIO 0 interrupt. More... | |
QM_ISR_DECLARE (qm_i2c_0_irq_isr) | |
ISR for I2C 0 irq mode transfer interrupt. More... | |
QM_ISR_DECLARE (qm_i2c_1_irq_isr) | |
ISR for I2C 1 irq mode transfer interrupt. More... | |
QM_ISR_DECLARE (qm_i2c_0_dma_isr) | |
ISR for I2C 0 dma mode transfer interrupt. More... | |
QM_ISR_DECLARE (qm_i2c_1_dma_isr) | |
ISR for I2C 1 dma mode transfer interrupt. More... | |
QM_ISR_DECLARE (qm_mailbox_0_isr) | |
ISR for Mailbox interrupt. More... | |
QM_ISR_DECLARE (qm_sram_mpr_0_isr) | |
ISR for Memory Protection Region interrupt. More... | |
QM_ISR_DECLARE (qm_pic_timer_0_isr) | |
ISR for PIC Timer interrupt. More... | |
QM_ISR_DECLARE (qm_pwm_0_isr_0) | |
ISR for PWM 0 Channel 0 interrupt. More... | |
QM_ISR_DECLARE (qm_pwm_0_isr_1) | |
ISR for PWM 0 channel 1 interrupt. More... | |
QM_ISR_DECLARE (qm_pwm_0_isr_2) | |
ISR for PWM 0 channel 2 interrupt. More... | |
QM_ISR_DECLARE (qm_pwm_0_isr_3) | |
ISR for PWM 0 channel 3 interrupt. More... | |
QM_ISR_DECLARE (qm_rtc_0_isr) | |
ISR for RTC 0 interrupt. More... | |
QM_ISR_DECLARE (qm_spi_master_0_isr) | |
ISR for SPI Master 0 interrupt. More... | |
QM_ISR_DECLARE (qm_spi_master_1_isr) | |
ISR for SPI Master 1 interrupt. More... | |
QM_ISR_DECLARE (qm_spi_slave_0_isr) | |
ISR for SPI Slave 0 interrupt. More... | |
QM_ISR_DECLARE (qm_uart_0_isr) | |
ISR for UART 0 interrupt. More... | |
QM_ISR_DECLARE (qm_uart_1_isr) | |
ISR for UART 1 interrupt. More... | |
QM_ISR_DECLARE (qm_wdt_0_isr) | |
ISR for WDT 0 interrupt. More... | |
QM_ISR_DECLARE (qm_wdt_1_isr) | |
ISR for WDT 1 interrupt. More... | |
QM_ISR_DECLARE (qm_usb_0_isr) | |
ISR for USB 0 interrupt. More... | |
Interrupt Service Routines.
QM_ISR_DECLARE | ( | qm_adc_0_cal_isr | ) |
QM_ISR_DECLARE | ( | qm_adc_0_pwr_isr | ) |
QM_ISR_DECLARE | ( | qm_aonpt_0_isr | ) |
ISR for Always-on Periodic Timer 0 interrupt.
This function needs to be registered with
if IRQ based transfers are used.
Definition at line 103 of file qm_aon_counters.c.
References qm_power_soc_restore().
QM_ISR_DECLARE | ( | qm_comparator_0_isr | ) |
ISR for Analog Comparator 0 interrupt.
This function needs to be registered with
if IRQ based transfers are used.
Definition at line 17 of file qm_comparator.c.
References qm_power_soc_restore().
QM_ISR_DECLARE | ( | qm_dma_0_error_isr | ) |
QM_ISR_DECLARE | ( | qm_dma_0_isr_0 | ) |
ISR for DMA channel 0 interrupt.
This function needs to be registered with
if IRQ based transfers are used.
Definition at line 158 of file qm_dma.c.
References QM_DMA_0, and QM_DMA_CHANNEL_0.
QM_ISR_DECLARE | ( | qm_dma_0_isr_1 | ) |
ISR for DMA channel 1 interrupt.
This function needs to be registered with
if IRQ based transfers are used.
Definition at line 164 of file qm_dma.c.
References QM_DMA_0, and QM_DMA_CHANNEL_1.
QM_ISR_DECLARE | ( | qm_dma_0_isr_2 | ) |
ISR for DMA channel 2 interrupt.
This function needs to be registered with
if IRQ based transfers are used.
Definition at line 171 of file qm_dma.c.
References QM_DMA_0, and QM_DMA_CHANNEL_2.
QM_ISR_DECLARE | ( | qm_dma_0_isr_3 | ) |
ISR for DMA channel 3 interrupt.
This function needs to be registered with
if IRQ based transfers are used.
Definition at line 177 of file qm_dma.c.
References QM_DMA_0, and QM_DMA_CHANNEL_3.
QM_ISR_DECLARE | ( | qm_dma_0_isr_4 | ) |
ISR for DMA channel 4 interrupt.
This function needs to be registered with
if IRQ based transfers are used.
Definition at line 183 of file qm_dma.c.
References QM_DMA_0, and QM_DMA_CHANNEL_4.
QM_ISR_DECLARE | ( | qm_dma_0_isr_5 | ) |
ISR for DMA channel 5 interrupt.
This function needs to be registered with
if IRQ based transfers are used.
Definition at line 189 of file qm_dma.c.
References QM_DMA_0, and QM_DMA_CHANNEL_5.
QM_ISR_DECLARE | ( | qm_dma_0_isr_6 | ) |
ISR for DMA channel 6 interrupt.
This function needs to be registered with
if IRQ based transfers are used.
Definition at line 195 of file qm_dma.c.
References QM_DMA_0, and QM_DMA_CHANNEL_6.
QM_ISR_DECLARE | ( | qm_dma_0_isr_7 | ) |
ISR for DMA 0 channel 7 interrupt.
This function needs to be registered with
if IRQ based transfers are used.
Definition at line 201 of file qm_dma.c.
References QM_DMA_0, and QM_DMA_CHANNEL_7.
QM_ISR_DECLARE | ( | qm_flash_mpr_0_isr | ) |
QM_ISR_DECLARE | ( | qm_flash_mpr_1_isr | ) |
QM_ISR_DECLARE | ( | qm_gpio_0_isr | ) |
QM_ISR_DECLARE | ( | qm_aon_gpio_0_isr | ) |
QM_ISR_DECLARE | ( | qm_i2c_0_irq_isr | ) |
QM_ISR_DECLARE | ( | qm_i2c_1_irq_isr | ) |
QM_ISR_DECLARE | ( | qm_i2c_0_dma_isr | ) |
QM_ISR_DECLARE | ( | qm_i2c_1_dma_isr | ) |
QM_ISR_DECLARE | ( | qm_mailbox_0_isr | ) |
ISR for Mailbox interrupt.
This function needs to be registered with
if IRQ based transfers are used.
Definition at line 66 of file qm_mailbox_se.c.
QM_ISR_DECLARE | ( | qm_sram_mpr_0_isr | ) |
QM_ISR_DECLARE | ( | qm_pic_timer_0_isr | ) |
ISR for PIC Timer interrupt.
On Quark Microcontroller D2000 Development Platform, this function needs to be registered with:
if IRQ based transfers are used.
On Quark SE, this function needs to be registered with:
if IRQ based transfers are used.
Definition at line 27 of file qm_pic_timer.c.
QM_ISR_DECLARE | ( | qm_pwm_0_isr_0 | ) |
ISR for PWM 0 Channel 0 interrupt.
If there is only one interrupt per controller this ISR handles all channel interrupts.
This function needs to be registered with
if IRQ based transfers are used.
Definition at line 62 of file qm_pwm.c.
References qm_pwm_channel_t::eoi, qm_pwm_reg_t::timer, and qm_pwm_reg_t::timersintstatus.
QM_ISR_DECLARE | ( | qm_pwm_0_isr_1 | ) |
QM_ISR_DECLARE | ( | qm_pwm_0_isr_2 | ) |
QM_ISR_DECLARE | ( | qm_pwm_0_isr_3 | ) |
QM_ISR_DECLARE | ( | qm_rtc_0_isr | ) |
ISR for RTC 0 interrupt.
This function needs to be registered with
if IRQ based transfers are used.
Definition at line 18 of file qm_rtc.c.
References qm_power_soc_restore().
QM_ISR_DECLARE | ( | qm_spi_master_0_isr | ) |
QM_ISR_DECLARE | ( | qm_spi_master_1_isr | ) |
QM_ISR_DECLARE | ( | qm_spi_slave_0_isr | ) |
QM_ISR_DECLARE | ( | qm_uart_0_isr | ) |
QM_ISR_DECLARE | ( | qm_uart_1_isr | ) |
QM_ISR_DECLARE | ( | qm_wdt_0_isr | ) |
QM_ISR_DECLARE | ( | qm_wdt_1_isr | ) |