10 #include "qm_soc_regs.h"
20 #define QM_I2C_SS_50_DC_NS (5000)
21 #define QM_I2C_FS_50_DC_NS (1250)
22 #define QM_I2C_FSP_50_DC_NS (500)
25 #define QM_I2C_MIN_SS_NS (4700)
26 #define QM_I2C_MIN_FS_NS (1300)
27 #define QM_I2C_MIN_FSP_NS (500)
30 #define DATA_COMMAND_READ_COMMAND_BYTE (QM_I2C_IC_DATA_CMD_READ >> 8)
31 #define DATA_COMMAND_STOP_BIT_BYTE (QM_I2C_IC_DATA_CMD_STOP_BIT_CTRL >> 8)
93 QM_I2C_STOP_DETECTED = BIT(25),
194 const uint16_t lo_cnt,
const uint16_t hi_cnt);
228 const uint8_t *
const data, uint32_t len,
249 uint8_t *
const data, uint32_t len,
const bool stop,
271 const uint16_t slave_addr);
393 const uint16_t slave_addr);
High Speed with restart disabled.
int qm_i2c_master_dma_transfer(const qm_i2c_t i2c, qm_i2c_transfer_t *const xfer, const uint16_t slave_addr)
Perform a DMA based master transfer on the I2C bus.
int qm_i2c_save_context(const qm_i2c_t i2c, qm_i2c_context_t *const ctx)
Save I2C context.
uint32_t tx_len
Write data length.
qm_i2c_speed_t speed
Standard, fast or fast plus mode.
int qm_i2c_master_write(const qm_i2c_t i2c, const uint16_t slave_addr, const uint8_t *const data, uint32_t len, const bool stop, qm_i2c_status_t *const status)
Master write on I2C.
int qm_i2c_master_read(const qm_i2c_t i2c, const uint16_t slave_addr, uint8_t *const data, uint32_t len, const bool stop, qm_i2c_status_t *const status)
Master read of I2C.
int qm_i2c_set_config(const qm_i2c_t i2c, const qm_i2c_config_t *const cfg)
Set I2C configuration.
int qm_i2c_set_speed(const qm_i2c_t i2c, const qm_i2c_speed_t speed, const uint16_t lo_cnt, const uint16_t hi_cnt)
Set I2C speed.
void * callback_data
User callback data.
qm_i2c_slave_stop_t stop_detect_behaviour
Slave stop detect behaviour.
Interrupt regardless of whether this slave is addressed or not.
int qm_i2c_dma_channel_config(const qm_i2c_t i2c, const qm_dma_t dma_controller_id, const qm_dma_channel_id_t channel_id, const qm_dma_channel_direction_t direction)
Configure a DMA channel with a specific transfer direction.
bool stop
Master: Generate STOP.
int qm_i2c_irq_transfer_terminate(const qm_i2c_t i2c)
Terminate I2C IRQ transfer.
qm_i2c_addr_t
QM I2C addressing type.
uint16_t slave_addr
I2C address when in slave mode.
qm_i2c_status_t
I2C status type.
int qm_i2c_master_irq_transfer(const qm_i2c_t i2c, const qm_i2c_transfer_t *const xfer, const uint16_t slave_addr)
Interrupt based master transfer on I2C.
qm_i2c_speed_t
QM I2C speed type.
int qm_i2c_get_status(const qm_i2c_t i2c, qm_i2c_status_t *const status)
Retrieve I2C bus status.
int qm_i2c_slave_irq_transfer(const qm_i2c_t i2c, volatile const qm_i2c_transfer_t *const xfer)
Interrupt based slave transfer on I2C.
qm_i2c_mode_t
QM I2C master / slave mode type.
Start or restart detected.
qm_i2c_slave_stop_t
QM I2C slave stop detect behaviour.
10-bit address read and restart disabled.
qm_i2c_mode_t mode
Master or slave mode.
int qm_i2c_slave_dma_transfer(const qm_i2c_t i2c, const qm_i2c_transfer_t *const xfer)
Perform a DMA based slave transfer on the I2C bus.
int qm_i2c_slave_irq_transfer_update(const qm_i2c_t i2c, volatile const qm_i2c_transfer_t *const xfer)
I2C interrupt based slave transfer buffer update.
qm_dma_channel_direction_t
DMA channel direction.
uint32_t rx_len
Read buffer length.
Trigger interrupt only if this slave is being addressed.
10-bit second address byte address noack.
qm_i2c_t
Number of I2C controllers.
I2C context to be saved between sleep/resume.
Standard mode (100 Kbps).
int qm_i2c_dma_transfer_terminate(const qm_i2c_t i2c)
Terminate any DMA transfer going on on the controller.
qm_dma_channel_id_t
DMA channel IDs.
High Speed master ID ACK.
int qm_i2c_restore_context(const qm_i2c_t i2c, const qm_i2c_context_t *const ctx)
Restore I2C context.
qm_i2c_addr_t address_mode
7 bit or 10 bit addressing.