6 #include "qm_soc_regs.h"
7 #include "qm_interrupt_router.h"
8 #include "qm_interrupt_router_regs.h"
11 #define INTERRUPT_ROUTER_LMT_INT_MASK_BASE \
12 (&QM_INTERRUPT_ROUTER->i2c_master_0_int_mask)
14 void _qm_ir_unmask_int(uint32_t irq, uint32_t register_offset)
16 uint32_t *interrupt_router_intmask;
19 interrupt_router_intmask =
20 (uint32_t *)INTERRUPT_ROUTER_LMT_INT_MASK_BASE + register_offset;
22 if (!QM_IR_INT_LOCK_MASK(*interrupt_router_intmask)) {
24 case QM_IRQ_COMPARATOR_0_INT:
30 QM_INTERRUPT_ROUTER->comparator_0_ss_int_mask &=
33 QM_INTERRUPT_ROUTER->comparator_0_host_int_mask &=
37 case QM_IRQ_MAILBOX_0_INT:
40 case QM_IRQ_DMA_0_ERROR_INT:
46 *interrupt_router_intmask &= ~QM_IR_DMA_ERROR_SS_MASK;
48 *interrupt_router_intmask &= ~QM_IR_DMA_ERROR_HOST_MASK;
52 QM_IR_UNMASK_INTERRUPTS(*interrupt_router_intmask);
58 void _qm_ir_mask_int(uint32_t irq, uint32_t register_offset)
60 uint32_t *interrupt_router_intmask;
63 interrupt_router_intmask =
64 (uint32_t *)INTERRUPT_ROUTER_LMT_INT_MASK_BASE + register_offset;
67 if (!QM_IR_INT_LOCK_MASK(*interrupt_router_intmask)) {
69 case QM_IRQ_COMPARATOR_0_INT:
71 QM_INTERRUPT_ROUTER->comparator_0_ss_int_mask |=
74 QM_INTERRUPT_ROUTER->comparator_0_host_int_mask |=
78 case QM_IRQ_MAILBOX_0_INT:
81 case QM_IRQ_DMA_0_ERROR_INT:
87 *interrupt_router_intmask |= QM_IR_DMA_ERROR_SS_MASK;
89 *interrupt_router_intmask |= QM_IR_DMA_ERROR_HOST_MASK;
93 QM_IR_MASK_INTERRUPTS(*interrupt_router_intmask);