Intel® Quark™ Microcontroller Software Interface
1.4.0
Intel® Quark™ Microcontroller BSP
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Clock Management for Sensor Subsystem. More...
Enumerations | |
enum | ss_clk_periph_t { SS_CLK_PERIPH_ADC = BIT(31), SS_CLK_PERIPH_I2C_1 = BIT(30), SS_CLK_PERIPH_I2C_0 = BIT(29), SS_CLK_PERIPH_SPI_1 = BIT(28), SS_CLK_PERIPH_SPI_0 = BIT(27), SS_CLK_PERIPH_GPIO_1 = BIT(1), SS_CLK_PERIPH_GPIO_0 = BIT(0) } |
Peripheral clocks selection type. More... | |
Functions | |
int | ss_clk_gpio_enable (const qm_ss_gpio_t gpio) |
Enable clocking for SS GPIO peripheral. More... | |
int | ss_clk_gpio_disable (const qm_ss_gpio_t gpio) |
Disable clocking for SS GPIO peripheral. More... | |
int | ss_clk_spi_enable (const qm_ss_spi_t spi) |
Enable clocking for SS SPI peripheral. More... | |
int | ss_clk_spi_disable (const qm_ss_spi_t spi) |
Disable clocking for SS SPI peripheral. More... | |
int | ss_clk_i2c_enable (const qm_ss_i2c_t i2c) |
Enable clocking for SS I2C peripheral. More... | |
int | ss_clk_i2c_disable (const qm_ss_i2c_t i2c) |
Disable clocking for SS I2C peripheral. More... | |
int | ss_clk_adc_enable (void) |
Enable the SS ADC clock. More... | |
int | ss_clk_adc_disable (void) |
Disable the SS ADC clock. More... | |
int | ss_clk_adc_set_div (const uint32_t div) |
Set clock divisor for SS ADC. More... | |
Clock Management for Sensor Subsystem.
The clock distribution has three level of gating:
enum ss_clk_periph_t |
Peripheral clocks selection type.
int ss_clk_adc_disable | ( | void | ) |
Disable the SS ADC clock.
0 | on success. |
Definition at line 68 of file ss_clk.c.
References QM_SS_ADC_CTRL.
int ss_clk_adc_enable | ( | void | ) |
Enable the SS ADC clock.
0 | on success. |
Definition at line 60 of file ss_clk.c.
References QM_SS_ADC_CTRL.
int ss_clk_adc_set_div | ( | const uint32_t | div | ) |
Set clock divisor for SS ADC.
Note: If the system clock speed is changed, the divisor must be recalculated. The minimum supported speed for the SS ADC is 0.14 MHz. So for a system clock speed of 1 MHz, the max value of div is 7, and for 32 MHz, the max value is
[in] | div | ADC clock divider value. |
0 | on success. |
Negative | errno for possible error codes. |
Definition at line 76 of file ss_clk.c.
References clk_sys_get_ticks_per_us(), and QM_SS_ADC_DIVSEQSTAT.
int ss_clk_gpio_disable | ( | const qm_ss_gpio_t | gpio | ) |
int ss_clk_gpio_enable | ( | const qm_ss_gpio_t | gpio | ) |
int ss_clk_i2c_disable | ( | const qm_ss_i2c_t | i2c | ) |
int ss_clk_i2c_enable | ( | const qm_ss_i2c_t | i2c | ) |
int ss_clk_spi_disable | ( | const qm_ss_spi_t | spi | ) |
Disable clocking for SS SPI peripheral.
[in] | spi | SPI port index. |
0 | on success. |
Negative | errno for possible error codes. |
Definition at line 36 of file ss_clk.c.
References QM_SS_SPI_0, and QM_SS_SPI_CTRL.
int ss_clk_spi_enable | ( | const qm_ss_spi_t | spi | ) |
Enable clocking for SS SPI peripheral.
[in] | spi | SPI port index. |
0 | on success. |
Negative | errno for possible error codes. |
Definition at line 28 of file ss_clk.c.
References QM_SS_SPI_0, and QM_SS_SPI_CTRL.