Intel® Quark™ Microcontroller Software Interface  1.4.0
Intel® Quark™ Microcontroller BSP
qm_mpr.c
1 /*
2  * {% copyright %}
3  */
4 
5 #include "qm_mpr.h"
6 #include "qm_interrupt.h"
7 #include "qm_interrupt_router.h"
8 
9 #define ADDRESS_MASK_7_BIT (0x7F)
10 
11 static void (*callback)(void *data);
12 static void *callback_data;
13 
14 QM_ISR_DECLARE(qm_sram_mpr_0_isr)
15 {
16  if (callback) {
17  (*callback)(callback_data);
18  }
19  QM_MPR->mpr_vsts = QM_MPR_VSTS_VALID;
20 
21  QM_ISR_EOI(QM_IRQ_SRAM_MPR_0_INT_VECTOR);
22 }
23 
24 int qm_mpr_set_config(const qm_mpr_id_t id, const qm_mpr_config_t *const cfg)
25 {
26  QM_CHECK(id < QM_MPR_NUM, -EINVAL);
27  QM_CHECK(cfg != NULL, -EINVAL);
28 
29  QM_MPR->mpr_cfg[id] &= ~QM_MPR_EN_LOCK_MASK;
30 
31  QM_MPR->mpr_cfg[id] =
32  (cfg->agent_write_en_mask << QM_MPR_WR_EN_OFFSET) |
33  (cfg->agent_read_en_mask << QM_MPR_RD_EN_OFFSET) |
34  /* MPR Upper bound 16:10 */
35  ((cfg->up_bound & ADDRESS_MASK_7_BIT) << QM_MPR_UP_BOUND_OFFSET)
36  /* MPR Lower bound 6:0 */
37  |
38  cfg->low_bound;
39 
40  /* enable/lock */
41  QM_MPR->mpr_cfg[id] |= (cfg->en_lock_mask << QM_MPR_EN_LOCK_OFFSET);
42  return 0;
43 }
44 #if (QM_SENSOR)
45 int qm_mpr_set_violation_policy(const qm_mpr_viol_mode_t mode,
46  qm_mpr_callback_t callback_fn, void *cb_data)
47 {
48  QM_CHECK(mode <= MPR_VIOL_MODE_PROBE, -EINVAL);
49  /* interrupt mode */
50  if (MPR_VIOL_MODE_INTERRUPT == mode) {
51  callback = callback_fn;
52  callback_data = cb_data;
53 
54  /* unmask interrupt */
55  QM_IR_UNMASK_INTERRUPTS(
56  QM_INTERRUPT_ROUTER->sram_mpr_0_int_mask);
57 
58  QM_IR_MASK_HALTS(QM_INTERRUPT_ROUTER->sram_mpr_0_int_mask);
59 
60  QM_SCSS_SS->ss_cfg &= ~QM_SS_STS_HALT_INTERRUPT_REDIRECTION;
61  }
62 
63  /* probe or reset mode */
64  else {
65  /* mask interrupt */
66  QM_IR_MASK_INTERRUPTS(QM_INTERRUPT_ROUTER->sram_mpr_0_int_mask);
67 
68  QM_IR_UNMASK_HALTS(QM_INTERRUPT_ROUTER->sram_mpr_0_int_mask);
69 
70  if (MPR_VIOL_MODE_PROBE == mode) {
71 
72  /* When an enabled host halt interrupt occurs, this bit
73  * determines if the interrupt event triggers a warm
74  * reset
75  * or an entry into Probe Mode.
76  * 0b : Warm Reset
77  * 1b : Probe Mode Entry
78  */
79  QM_SCSS_SS->ss_cfg |=
80  QM_SS_STS_HALT_INTERRUPT_REDIRECTION;
81  } else {
82  QM_SCSS_SS->ss_cfg &=
83  ~QM_SS_STS_HALT_INTERRUPT_REDIRECTION;
84  }
85  }
86  return 0;
87 }
88 #else
89 int qm_mpr_set_violation_policy(const qm_mpr_viol_mode_t mode,
90  qm_mpr_callback_t callback_fn, void *cb_data)
91 {
92  QM_CHECK(mode <= MPR_VIOL_MODE_PROBE, -EINVAL);
93  /* interrupt mode */
94  if (MPR_VIOL_MODE_INTERRUPT == mode) {
95  callback = callback_fn;
96  callback_data = cb_data;
97 
98  /* unmask interrupt */
99  QM_IR_UNMASK_INT(QM_IRQ_SRAM_MPR_0_INT);
100 
101  QM_IR_MASK_HALTS(QM_INTERRUPT_ROUTER->sram_mpr_0_int_mask);
102  }
103 
104  /* probe or reset mode */
105  else {
106  /* mask interrupt */
107  QM_IR_MASK_INT(QM_IRQ_SRAM_MPR_0_INT);
108 
109  QM_IR_UNMASK_HALTS(QM_INTERRUPT_ROUTER->sram_mpr_0_int_mask);
110 
111  if (MPR_VIOL_MODE_PROBE == mode) {
112 
113  /* When an enabled host halt interrupt occurs, this bit
114  * determines if the interrupt event triggers a warm
115  * reset
116  * or an entry into Probe Mode.
117  * 0b : Warm Reset
118  * 1b : Probe Mode Entry
119  */
120  QM_SCSS_PMU->p_sts |=
121  QM_P_STS_HALT_INTERRUPT_REDIRECTION;
122  } else {
123  QM_SCSS_PMU->p_sts &=
124  ~QM_P_STS_HALT_INTERRUPT_REDIRECTION;
125  }
126  }
127  return 0;
128 }
129 #endif /* QM_SENSOR */
130 
131 #if (ENABLE_RESTORE_CONTEXT)
133 {
134  QM_CHECK(ctx != NULL, -EINVAL);
135  int i;
136 
137  qm_mpr_reg_t *const controller = QM_MPR;
138 
139  for (i = 0; i < QM_MPR_NUM; i++) {
140  ctx->mpr_cfg[i] = controller->mpr_cfg[i];
141  }
142 
143  return 0;
144 }
145 
147 {
148  QM_CHECK(ctx != NULL, -EINVAL);
149  int i;
150 
151  qm_mpr_reg_t *const controller = QM_MPR;
152 
153  for (i = 0; i < QM_MPR_NUM; i++) {
154  controller->mpr_cfg[i] = ctx->mpr_cfg[i];
155  }
156 
157  return 0;
158 }
159 #else
161 {
162  (void)ctx;
163 
164  return 0;
165 }
166 
168 {
169  (void)ctx;
170 
171  return 0;
172 }
173 #endif /* ENABLE_RESTORE_CONTEXT */
int qm_mpr_set_violation_policy(const qm_mpr_viol_mode_t mode, qm_mpr_callback_t callback_fn, void *cb_data)
Configure MPR violation behaviour.
Definition: qm_mpr.c:45
qm_mpr_id_t
Definition: qm_soc_regs.h:1286
int qm_mpr_set_config(const qm_mpr_id_t id, const qm_mpr_config_t *const cfg)
Configure SRAM controller's Memory Protection Region.
Definition: qm_mpr.c:24
QM_RW uint32_t mpr_cfg[4]
MPR CFG.
Definition: qm_soc_regs.h:1296
MPR context type.
Definition: qm_soc_regs.h:1629
Number of Memory Protection Regions.
Definition: qm_soc_regs.h:1291
uint8_t en_lock_mask
Enable/lock bitmask.
Definition: qm_mpr.h:35
int qm_mpr_restore_context(const qm_mpr_context_t *const ctx)
Restore MPR context.
Definition: qm_mpr.c:146
QM_ISR_DECLARE(qm_sram_mpr_0_isr)
ISR for Memory Protection Region interrupt.
Definition: qm_mpr.c:14
uint8_t low_bound
1KB-aligned lower addr
Definition: qm_mpr.h:39
uint8_t up_bound
1KB-aligned upper addr
Definition: qm_mpr.h:38
int qm_mpr_save_context(qm_mpr_context_t *const ctx)
Save MPR context.
Definition: qm_mpr.c:132
uint8_t agent_write_en_mask
Per-agent write enable bitmask.
Definition: qm_mpr.h:37
Memory Protection Region register map.
Definition: qm_soc_regs.h:1295
SRAM Memory Protection Region configuration type.
Definition: qm_mpr.h:34
uint32_t mpr_cfg[QM_MPR_NUM]
MPR Configuration Register.
Definition: qm_soc_regs.h:1630
uint8_t agent_read_en_mask
Per-agent read enable bitmask.
Definition: qm_mpr.h:36