============================================================================= Intel(R) Server Board SE7501BR2 ============================================================================= INTEL Enterprise Platform & Services Marketing Intel Corporation 2111 N.E. 25th Avenue, Hillsboro, OR 97124 USA ============================================================================= DATE: September 15th, 2004 TO: Intel server platform SE7501BR2 customers SUBJECT: Intel SE7501BR2 BIOS Release Notes ver P20 20.00 - Build # 0079 ============================================================================= LEGAL INFORMATION ============================================================================= Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Intel is a registered trademark of Intel Corporation. *Other names and brands are the property of their respective owners. Copyright (C) 2004 Intel Corporation. ============================================================================= ABOUT THIS BIOS RELEASE ============================================================================= Build # : 0079 Build Stamp : SBR20.86B.0079.P20.0409150850 Build Date : September 15th, 2004 ============================================================================= BIOS COMPONENTS/CONTENTS ============================================================================= Processor supported: Intel(R) Xeon(TM) Processors with 512KB L2 Cache and Intel(R) Xeon(TM) Processors with 512KB L2 Cache and 1M L3 Cache. Microcode update versions: CPUID Microcode Stepping 0F24h 1F B0 0F27h 38 C1 0F29h 2D D1 0F25h 29 M0 System Hardware Configuration Supported: SE7501BR2 Production boards (A95686- 502 or later) ============================================================================= SYSTEM FIRMWARE REQUIREMENTS/REVISIONS ============================================================================= BMC FW : 1.17 or higher FRU/SDR : 5.6.J or higher HSC : 0.10 On-Board Component Option ROM Versions: Adaptec 7901 SCSI : 4.30S2 ATI Rage XL VGA : 09A Intel Pro/100 NIC : 4.1.15 Intel Pro/1000 NIC : 1.2.22 ============================================================================= INSTALLATION NOTES ============================================================================= IMPORTANT NOTES: 1. SE7501BR2 BIOS is not compatible with Windows 98 or Windows XP bootable diskettes. Please use DOS 6.22 booting diskette or ROM-DOS booting diskette. 2. Firmware must be updated before BIOS. If it isn't, the BIOS update may or may not work. Refer to the System Firmware Requirements section above. 3. CMOS should always be cleared after a BIOS update. But if your current BIOS version is newer than P08-0065, you don't need to clear CMOS because CMOS Map has not changed since then. UPDATE INSTRUCTIONS: This instructions do not apply when running the update directly from the Software Update Package Menu. In that event, instructions displayed in the screen should be followed. The instructions below only applies when creating a BIOS update disk. 1. Create a BIOS update disk; ensure to use a bootable floppy. 2. Boot the SE7501BR2 server board with floppy created in step #2. 3. At the DOS prompt type 1 (or 1.BAT) and press . The update will show two progress bars. After the second progress bar has reached 100 percent, the system will reboot (typically under 3 minutes). 4. Once the update is complete, proceed to clear CMOS. CLEARING CMOS: 1. Power down system and disconnect AC power. 2. Move the CMOS Clear jumper (J1H1) from BMC Control position (pins 1-2) to Force Erase position (pins 2-3). 3. Power up the system and allow BIOS to POST. A message will be displayed indicating "CMOS has been cleared by jumper". If applicable, enter BIOS setup by pressing F2 and change any BIOS user settings; press F10 to Save Changes and Exit. 4. Power down system and disconnect AC power. 5. Move the CMOS Clear jumper (J1H1) back to BMC Control position (pins 1-2). 6. Power up the system and boot normally. ============================================================================= KNOWN ISSUES/WORKAROUNDS ============================================================================= 1. With Intel(R) Xeon(TM) processors with 533MHz FSB, you must use DDR266 for all memory banks on a 533 system. 2. To enable PCI PERR logging, the user must enable "Assert NMI on PERR" in BIOS setup. 3. The clock to a PCI slot is turned off if no card is present in the slot. Port 80h cards are not considered valid PCI cards, thus if a Port 80h card is plugged into PCI slots 5 or 6 the last port 80h value that will be seen is F2h before the clock is turned off to these slots. A workaround to prevent the clocks from being turned off on PCI Slots 5 and 6 is to enable Num Lock under BIOS setup. 4. PCI-X clock speed: # Slots Channel Channel A Channel B Populated (AIC-7901) 0 PCI-X/100MHz PCI-X/133MHz 1 PCI-X/100MHz PCI-X/133MHz 2 PCI-X/100MHz PCI-X/100MHz ============================================================================= FEATURES ADDED ============================================================================= Build P20-0079: - Added new microcode update for D1 stepping of Intel(R) Xeon(TM) processors with 512KB L2 Cache and M0 stepping of the Intel(R) Xeon(TM) processors with 512KB L2 Cache and 1MB L3 Cache. - Added routine to display the Product Manufacturer Name from the FRU to the top line of the POST Diagnostic Screen. If the string (from the FRU) is read as 'Intel', only a blank line will be shown, if any other string is read, it will be displayed. - Added the latest IBA 4.1.15 (On-board Intel Pro/100 NIC) and 1.2.22 (On-board Intel Pro/1000 NIC). - Added support for Booting from PQI Secure DOM. Build P19-0078: - None. Build reserved, not released to general public. Build P18-0077: - None. Build reserved, not released to general public. Build P17-0076: - None. Build reserved, not released to general public. Build P16-0075: - Added new microcode update for M0 stepping of the Intel(R) Xeon(TM) processors with 512KB L2 Cache and 1MB L3 Cache. Build P15-0074: - Added new microcode update for B0/D1 stepping of Intel(R) Xeon(TM) processors with 512KB L2 Cache and M0 stepping of the Intel(R)Xeon(TM) processors with 512KB L2 Cache and 1MB L3 Cache. - AIC-7901 SCSI option ROM 4.30S2 replaces previous version 4.10.03S2. Build P14-0073: - None. Build P13-0072: - Added new microcode update for C1/D1 stepping of Intel(R) Xeon(TM) processors with 512KB L2 Cache. - Added support for upcomming processor speeds. Build P12-0071: - None. Build reserved, not released to general public. Build P11-0070: - New microcode (revision 11) added to support the M0 stepping of the Intel(R) Xeon(TM) processors with 512KB L2 Cache and 1MB L3 Cache. - Added fix for MCH Errata3: System Hung After Asynchronous Reset To DIMM. Build P10-0068: - None. Build reserved, not released to general public. Build P09-0067: - None. Build reserved, not released to general public. Build P08-0065: - None. Build reserved, not released to general public. Build P07-0064: - None. Build reserved, not released to general public. Build P06-0063: - New microcode update (revision 0F) for D1 stepping of Intel(R) Xeon(TM) processors with 512KB L2 Cache was added. - SC1350 chassis 1U riser support is added. - AIC-7901 SCSI option ROM 4.10.03S2 replaces previous version 4.10.01S2. Build P05-0051: - As required in Intel® NetBurst(TM) Micro-Architecture BIOS Writer's Guide rev 1.6, BIOS P05 enables Machine Check Architecture handler. - 48-bit LBA mode is supported. This is done to support IDE hard drive sizes beyond the 128GB barrier. - New microcode update (revision 1D) for B0 stepping of Intel(R) Xeon(TM) processors with 512KB L2 Cache. Build P04-0047: - None. Build P03-0046 - SCM support was added. Build P02-0043: - Intel(R) E7501 Chipset memory reference code 1.01 was merged. ============================================================================= ISSUES FIXED ============================================================================= Build P20-0079: - Make Cache Line Size register (0Ch) have a value of 08h for add-in PCI cards as well, this fix will speed up the PCI performance numbers. - System hangs when NIC cable is removed in DOS. - Added new Prestonia CPU Patches for D1 (M02F2922) and M0 (M01F251E) steppings to address errata P72. - Added new Prestonia CPU Patches for D1 (M02F292D) and M0 (M01F2529) steppings to address errata P76. - The current state field of each PCI-X slot is reported as 'unknown' (instead of 'in use' or 'available' depending on the presence of a PCI card in the corresponding slot). Build P19-0078: - None. Build reserved, not released to general public. Build P18-0077: - None. Build reserved, not released to general public. Build P17-0076: - None. Build reserved, not released to general public. Build P16-0075: - Improper Bridge Initialization potentially creating I/O Bottleneck. Fixed by changing the P64H2 (both devices -- 29 and 31) cache line size register (0Ch) from a value of 10h to a value of 08h. This fix will dramatically speed up the PCI performance numbers as well. - PXE-E01 message reported when Onboard NIC is disabled. Fixed by skipping LAN console in dih_sys_config_done and skipping kill_lan_stack routine at the end of POST if NIC is disabled. Build P15-0074: - Ghost PCI slot 2 when a 1U riser is plugged in on Bryson/Kahana system. Fixed by placing a value in the FRU which the BIOS could read to determine if a 1U or 2U riser is present. - No AC-Link Parameter Option Available In BIOS Setup. Fixed by removing Externalfunction=check_sysbmc_proc2 from Q_POWER_FAILURE_OPTION declaration. - BIOS version information in W2K Advanced server is incorrect. Fixed by using ax instead of eax during analyzing BIOS version string. - Boot from USB devices works when Legacy USB set as KB only or KB and Mouse. Fixed by checking for Q_USB_LEGACY_ENABLE CMOS token and enumerating USB mass storage device only if the value of this token is set to "Auto". - Add "S" (SCSI SKU) or "D" (SCSI Depop) to end of SMBIOS Type 2 Product field. - With failed DIMM, incorrect errors are displayed in POST and SEL. Fixed by adding single channel support codes to the following two procedures: get_failing_memory_socket_jmp_di, get_failing_memory_address_jmp_di. - SuSE 8.2/9.0 fails with HostRAID configuration on Bryson. Fixed by replacing previous AIC-7901 SCSI option ROM version 4.10.03S2 with 4.30S2. Build P14-0073: - Fixed improper L3 Cache Initialization which was leading to power cycling failures. Build P13-0072: - 3.06Ghz/533FSB M0 CPU power cycle failure exhibited in stress testing. - Invalid SMBIOS structure implementation for processors without L3 cache. - ERROR! 8193: displayed on systems configured with valid D1 & M0 mixed processor steppings. - BIOS logo incorrectly displayed after CMOS clear. - Corrected issue with certain ATAPI Tape Drives not working on U-DMA mode. Build P12-0071: - None. Build reserved, not released to general public. Build P11-0070: - POST error pause exhibited when system configured with ±1 mixed CPU stepping - DIMM error occurred on POST with certain 1GB DIMMs during AC or DC cycling test Build P10-0068: - None. Build reserved, not released to general public. Build P09-0067: - None. Build reserved, not released to general public. Build P08-0065: - None. Build reserved, not released to general public. Build P07-0064: - None. Build reserved, not released to general public. Build P06-0063: - Failed to create Service patition in USB HDD - Setting DAY field only in BIOS Setup after Battery reset results 01/01/1990 on next boot - Error message for memory configuration are different between FSB 400 MHz and 533 MHz. - Flash Update driver won't load under Microsoft Windows* with latest Bryson BIOS release Build P05-0051: - Netburst BWG rev 1.6 requires BIOS to implement an MCA handler. - Does not wake with Legacy Wake On LAN/PME/WOR, after told to go to standby from the Windows 2000 Start Task Bar Menu. - SEL log fills with single bit errors if extended memory test is enabled and there is a failing DIMM in xB. - Need BIOS support for 48-bit LBA to enable compatibility with IDE drives greater than 128GB in size. - Double bit errors logged in SEL or displayed in POST Error messages do not fully meet specification. - No SEL event is logged when settings are changed and saved in BIOS SETUP - When "Reset Config Data" in BIOS SETUP is selected, the "System Reconfigured" SEL event continues to be logged on subsequent boots. - After setting Serial Port Address to "disabed", "Redirection Port" is incorrect. - NIC2 can not PXE Boot if the higher device in boot priority has an active LAN connection. - Wake on PME by PCI Slot5/6 does not work correctly. - Late post FRB does not "Stay On" or "Power Off". - Support the second OEM Strings of DMI Type 11. - Unreported I/O test failure with Microsoft Windows* Server 2003. - System hangs during post with six FC adapters in PCI slots. - Ensure proper SCSI vendor/device ID in the SCSI PCI config space based on AIC-7901 with raid or without raid. - ACPI Errors test failure issue with Windows Server2003 HCT11.1. Build: P04-0047 - Proprietary 33 MHz PCI card not functional in PCI-X slots. - Exiting BIOS Setup after Front panel CMOS clear system prompts for power off. - Hard Disk Pre-Delay option of BIOS Setup doesn't work. - Can't detect SD-C2612 DVDROM and IDE HD on the same IDE channel. - USB LS120 will not read or write to a 1.44Mb floppy disk while booted to DOS. - Option ROM Disable in BIOS 20 Setup does not work with "bridged" adapters. - BIOS does not lock down the primary flash partition at the end of POST. - PCI BIOS function call GET_INT_ROUTE (0x0e) fails with a page fault. Build P03-0046 - Certain Serial Event Logs are not generated. - Setup Viewer I/F incorrect. - Few words in BIOS setup do not have foreign translations. - BMC asserts the CMOS clear request after Front Panel CMOS Clear. - Disabling NIC1 causes the W2K Found New Hardware Wizard to request SCSI drivers. Build P02-0043: - Need to update BIOS to memory reference code 1.01 - PS/2 keyboard not working in top PS/2 port when no PS/2 mouse is present - When CMOS is Cleared, DIMM BANK #1 & #2 information is set to Not Installed. - No POST error is displayed when configuring system with mismatch CPU speeds - When FRB Policy is set to "Retry 3 Times" in SETUP, the system does not work. - With only 1 Bank populated the system does not recognize SBE or DBE's - Events continue to be logged when Event Logging is disabled - Need to change MAX length of strings for DMI Type1 - Auto-rebooting running OB SCSI option ROM due to "Watchdog timer failed" - BIOS does not display the FSB speed during POST - POST displays "Legacy USB enabled" when USB Function is disabled ============================================================================= REFERENCE MATERIAL ============================================================================= Intel(R) Server Platform SE7501BR2 Technical Product Specification (TPS) [END OF BIOS RELEASE NOTES] ============================================================================= ABOUT THIS BMC RELEASE ============================================================================= Firmware Version: 1.19 Bootblock Version: 0.15 Build Date: July 17, 2004 Bootblock checksum: 5C2Dh Opcode checksum: 5A1FH ============================================================================= IMPORTANT NOTES ============================================================================= - BMC 1.19 is designed for use with FRUSDR 5.6.J and later. - No bootblock update is required when updating the board from BMC 1.11. This release has been configured to update BMC from BMC ver 1.11. Any board with BMC 1.10 or earlier will require to be updated to BMC 1.11 following BMC 1.11 release notes closely prior to updating this BMC release. - Beginning with BMC version 1.11, the BMC incorporates a "Platform ID" code in the PIA portion of the flash. This change was made to facilitate online update. Because of this change, when flashing from version 1.10 and earlier to version 1.11 or later, the DOS firmware update utility will issue the following error message: Platform IDs don't match in the Boot Block. The update cannot continue. The error message incorrectly identifies the area of the problem, it is the PIA not the boot block. To overcome this, include the -nopc switch on the update utility command line, as shown below: FWPIAUPD -ni -u -o -p -nopc SBR2_xxx.HEX The update batch files for firmware versions post 1.11 DO NOT include this -nopc switch, users will need to manually update the BMC if coming from a BMC version earlier than 1.11. ============================================================================= INSTALLATION NOTES ============================================================================= This instructions do not apply when running the update directly from the Software Update Package Menu. It only applies when creating a BMC update disk. 1. Insert floppy diskette created from SUP file into the floppy drive. The following three files must be contained on the floppy diskette: SBR2_xxx.hex Fwpiaupd.exe Update.bat 2. If needed, make the disk bootable by using MS-DOS/Win9x SYS command. 3. Insert floppy diskette created in step #1 into the floppy drive. 4. Boot from disk or execute update.bat manually 5. Wait till you see a confirmation on the screen that the update has completed 6. Install the latest SE7501BR2 FRU/SDR package. Executing the fwpiaupd utility with your own command switches is unsupported and may leave your baseboard in a non-operational state! ============================================================================= KNOWN ISSUES/WORKAROUNDS ============================================================================= - None. ============================================================================= FEATURES ADDED ============================================================================= Build 1.19: - None. Build 1.18: - None. Build 1.17: - None. Build 1.16: - BMC FW and FRUSDR support added for the SR-1350E chassis (Full support for the SR-1350E chassis requires FRU/SDR 5.5.G) Build 1.15: - None. Build 1.14: - None. Build 1.13: - N/A; build not released. Build 1.12: - N/A; build not released. Build 1.11: - None. Build 1.10: - Support for new AML flash part 28F160C3BC70 was added. - Added support for the SC5200 BRP Chassis sensors. Build 1.09: - Support for the Hudson III BRP 450W 1 + 1 power supply unit was added. Full support for BRP chassis requires FRU/SDR 5.3.B. - Support for Get BMC Configuration command was added. ============================================================================= ISSUES FIXED ============================================================================= Build 1.19: - BMC CMOS clear is intermittent. - BMC stops monitoring fan if fan connection is changed when no AC is present. - COM2 noise causes serial devices to hang. Build 1.18: - Fan Redundancy sensor showing on non-redundant chassis in ISM. - FRUSDR 5.5.H does not signal FP LED for faults when selecting "Other". Build 1.17: - BMC does not support device SDRs. Reflect that in IPMI properly. - Changed CMOS clear detection form EQ 4000ms to GE4000ms. Build 1.16: - Added more one-shot action for beep code. - Fault LED on SC5200 Base and BRP does not go amber upon fan failure. - BMC FW shows Full Redundant after removing one PU. Build 1.15: - Pwr Unit 02 Redundancy lost during shutdown logged in SEL & results on Fault LED illumination when power off. Changed to update PS failure offset after validating power state for 450W 1+1 power cage. Build 1.14: - BMC ver 1.11 did not match the shipping configuration of the SC5200 HSRP power supply. BMC 1.11 required that power supplies be populated in 1, 2, 3 order. BMC 1.14 removes this restriction. Note that FRU & SDR package 5.5.D should also be used with BMC 1.14. - Removing fan 4 did not result in a fan boost or fault LED indication on the SC5200 Base and BRP chassis. - In certain circumstances, the BMC would return the wrong number of power supplies in response to the Get Power Supply State command. Build 1.13: - N/A; build not released. Build 1.12: - N/A; build not released. Build 1.11: - The chassis intrusion sensor would log a chassis intrusion event every time AC was applied regardless of whether the chassis was open or not. - When socket 603 processors were installed, the BMC would log temperature events after every time AC power was removed and reapplied. - In very rare conditions, the response to a clear SEL request was delayed up to 10 seconds, suspending BMC I/O traffic for this period. - Intermittent FRB timeouts and disabled CPUs. Corrected firmware power control algorithm. - DC power cycling problems. Front panel button rarely misses a single actuation, works on next use. Corrected firmware power control tables and algorithm. Build 1.10: - None. Build 1.09: - Processor1 temperature going low error in FSB400 CPU system. - BMC 1.08 Thermal trip on CPU 0 causes Thermal Trip and IERR error on CPU 1 - Firmware is still leaving the serial port over to the SIO when powered off - BMC - Periodic BMC Self Test errors being seen in manufacturing - BMC fails to dial up when alerting to the dial page. - BMC - Get Power Supply State returns the wrong number of power supplies - Sometimes BMC doesn't de-assert PS_PWR_ON_L on DC cycle - Need support for Hudson III BRP power Supply unit - BMC: Attempting exit from FTM when Op Code corrupted breaks SMS - Stack for the timer interrupt overflows in some conditions ============================================================================= REGARDING BOOT BLOCK UPDATES ============================================================================= The boot block on the BMC is write protected and should never be updated unless these release notes specifically call for a boot block update. Never use the -b or -boot switch on the command line. If the utility is run interactively, always answer NO to the "Update the boot block" question. If you do attempt to update the boot block while the write protection jumper is in place, the boot block will NOT be modified. However, when the utility attempts to verify that the code in the flash matches the code in the SBR2_xxx.HEX file, the verify will fail. Please note that this is a "false" warning - the boot block on the BMC is still perfectly fine since it is write protected. The reason the verify fails in this case is that each version of firmware places a time/date stamp of when the firmware was compiled into the boot block area of the SBR2_xxx.HEX file. It is this data that changes with each new file and causes the verify to fail. To perform a boot block update, do the following: 1. Power down the server, unplug the AC cord(s) and open the chassis. 2. Move the jumper from pins 1 & 2 on the J1J1 jumper block, to pins 2 & 3. The jumper block is near the Front Panel connector on the edge of the board. 3. Plug in the AC cord, power up and boot to DOS. 4. Enter the command: FWPIAUPD -ni -u -o -p -b SBR2_xxx.HEX OR Use the supplied Upd_boot.bat file 5. After the update completes, power down and unplug AC. 6. Replace the jumper you installed in step 2. 7. Close the chassis, plug in AC and boot normally. ============================================================================= REFERENCE MATERIAL ============================================================================= Intel(R) Server Platform SE7501BR2 Technical Product Specification Revision 1.0 [END OF BMC RELEASE NOTES] ============================================================================= ABOUT THIS FRUSDR RELEASE ============================================================================= This document describes some specifics of the Intel(R) server board SE7501BR2 FRU & SDR Utility Package Version 5.5.H. This utility is used for updating the server management subsystem product level Field Replacement Unit (FRU) and the Sensor Data Repository (SDR). ============================================================================= GENERAL INFORMATION ============================================================================= This utility is used to update the non-volatile storage device associated with the Baseboard Management Controller, which holds the SDR & FRU areas. The utility has the capability to generically handle FRU devices that may not be associated with the Baseboard Management Controller (BMC). Through the use of a configuration file, added features allow the user to control the execution path by probing hardware, requesting user input, and setting tags to provide filtering of FRU and SDR data. Multiple FRU and SDR files may also be processed at once. If the user receive an error concerning the FRU headers not matching, when trying to program a FRU file, this happens when the FRU file on the server is a non-compatible version with the one you are trying to program. In this case you should contact your vendor for support and get a system update package made to handle this problem. The FRUSDR utility supports IPMI 0.9, IPMI 1.0 and IPMI 1.5 specifications. Be aware that both the FRU and SDR file formats vary between these different implementations and are not completely backward compatible. The utility will work correctly on a IPMI 0.9, a IPMI 1.0 or a IPMI 1.5 system, but mixed IPMI solutions on systems are not supported except for IPMI 1.0 and 1.5 FRU devices. ============================================================================= DEPENDENCIES ============================================================================= - FRUSDR package 5.6.J should only be used with BIOS P15 or later, BMC 1.19 or later. - FRUSDR package 5.5.I should only be used with BMC 1.18 or later. - FRUSDR package 5.5.H should only be used with BMC 1.17 or later. - FRUSDR package 5.5.G should only be used with BMC 1.16 or later. - FRUSDR package 5.5.F should only be used with BMC 1.15 or later. - FRUSDR package 5.5.E should only be used with BMC 1.14 or later. - FRUSDR package 5.5.D should only be used with BMC 1.13 or later. - FRUSDR package 5.5.C should only be used with BMC 1.10 or later. - FRUSDR package 5.5.B should only be used with BMC 1.09 or later. - There are no known BIOS or SCSI Hot Swap Backplane controller dependencies. ============================================================================= KNOWN ISSUES/WORKAROUNDS ============================================================================= - None. ============================================================================= FEATURES ADDED ============================================================================= Version 5.6.J: - None. Version 5.5.I: - None. Version 5.5.H: - None. Version 5.5.G: - Support for the Intel SR1350-E chassis was added. Note that this chassis utilizes seven system fans which must be connected to the board's System Fan headers and CPU Fan Headers as described below. Following is a diagram of the SR1350-E chassis fans as seen from the front of the chassis. ______ ______ | || | | FAN7 || FAN6 | |______||______| ______ ______ ______ ______ ______ | | | || || || | | FAN5 | | FAN4 || FAN3 || FAN2 || FAN1 | |______| |______||______||______||______| Chassis Fan 1 (closest to P/S) connects to the board's "CPU1 FAN" header Fan 2 connects to "SYS FAN3" Fan 3 connects to "CPU2 FAN" header Fan 4 connects to "SYS FAN4" Fan 5 (closest to intrusion switch) connects to "SYS FAN5" Fan 6 (rear fan closest to the outer edge) connects to "SYS FAN1" Fan 7 (rear fan closest to IO shield) connects to "SYS FAN2" Version 5.5.F: - Added FRUSDR selection for IDE board (SCSI de-pop) to support the SE7501BR2 server board SKU that does not have on-board SCSI. All shipping boards PBA rev A895686-504 or earlier must select "Onboard SCSI" option. Version 5.5.E: - Added support for the Intel SC5250-E chassis. Note that this chassis utilizes 2 system fan headers. This FRUSDR when installed in an Intel SC5250-E will enable "SYS FAN 2" and "SYS FAN 5" fan sensors in the SE7501BR2 server board. In order to properly monitor the fans, the back fan must be connected to the "SYS FAN 2" header and the front hard drive fan must be connected to the "SYS FAN 5" header on the SE7501BR2 board. Version 5.5.D: - None. Version 5.5.C: - Added SMaRT Tool chassis name programming of BMC FRU for SC5200. - Modified Processor Vccp limits to support 3.06 GHz processors. Version 5.5.B: - Added support for the Intel SC5200 BRP chassis 1+1 redundant supply. - Enforced the BMC 1.11 requirement that power supplies be populated in 1,2,3 order. - Detect the SC5200 chassis by detecting front panel temp sensor rather than by questioning the user. ============================================================================= ISSUES FIXED ============================================================================= Version 5.6.J: - Added 1U/2U Riser FRU configuration to reflect different PCI slot numbers with different Chassis. - Fixed incorrect file revision info in SDR file. - Added BMC_REFRESH command in Master.cfg file. Version 5.5.I: - Removed fan redundancy event assertion for SC5200 BRP, BASE, SR1350-E, SC5250-E and 'Other' chassis configurations. - Corrected FP LED not indicating fault upon fan failure when selecting 'Other' during FRUSDR installation. Version 5.5.H: - Deleted display of unneeded fan messages from SR1350-E operation. - Corrected fan redundancy LED operation for SC5200 HSRP chassis. - Corrected display of fan redundancy in ISM for SC5200 HSRP chassis. - Changed SDR tag for SC5250-E. Version 5.5.G: - System Fault LED not indicating fault upon fan failure on SC5200 Base & BRP. Version 5.5.F: - Corrected fan redundancy table. - Removed OEM fan redundancy sensor and map records for all configurations except HSRP. - Changed power unit redundancy OEM SDR format. - Corrected ambient temperature control tables. Version 5.5.E: - None. Version 5.5.D: - Changed processor fan speed decoding to support 3.06 GHz processor fan sinks that can spin at up to 11,000 RPM. This change requires BMC 1.13 or later for correct fan speed decoding. - The name of the "Proc Hot" sensor was changed to "CPU Thermal Ctrl". - The name of the power system redundancy sensor was changed from 'Pwr Redund Lost' to 'Power Redundancy'. - Unplugging Sys Fan 4 on an SC5200 Base or BRP system did not cause a fan boost, this SDR package in conjunction with BMC 1.13 or later corrects this. - BMC 1.11 required power supplies to be inserted in a 1,2,3 order, earlier SDR packages enforced this rule. BMC 1.13 does not require this, and this SDR package no longer limits power supply installation. - The Config file no longer determines whether an Intel chassis is present based on detecting the front panel temperature sensor, the user is queried instead. Version 5.5.C: - None. Version 5.5.B: - None. ============================================================================= INSTALLATION NOTES ============================================================================= The FRUSDR Loader is meant to be used as a DOS application on a server. The utility should be placed onto a bootable DOS floppy and the system rebooted prior to and after using. There is no need to actually install the application on to a server. Running the utility in a Windows DOS box is not supported and will provide incorrect results. Normal Command Line Use: A:> FRUSDR -CFG MASTER.CFG Note: Programming the BMC FRU internal use area clears the SDR repository. Therefore, the SDR repository must be reprogrammed after programming the BMC. Upon completion of programming the FRU and SDR areas, remove the floppy disk and reboot the server. ---------------------------------------------------------------------------- PARSING THE COMMAND LINE ---------------------------------------------------------------------------- The FRUSDR Loader command line provides the following options: Usage: /? or /h Displays usage information. /d {smb,fru,sdr} Only displays requested area. /cfg filename.cfg Uses custom CFG file. /p Pause between blocks of data. Note: Users may alternatively use a '-' instead of the '/'. ---------------------------------------------------------------------------- DISPLAY FRU, SDR, and SMB INFORMATION ---------------------------------------------------------------------------- The SDR area can be displayed by using the -D SDR parameter with the FRUSDR command, such as FRUSDR -D SDR. The SM BIOS (SMB) area can be displayed with the -D SMB parameter with the FRUSDR command. Note: The system must be rebooted in order for the SM BIOS (SMB) changes to take effect. The -D FRU parameter will display the BMC FRU area by default. To view other FRU areas, additional addressing information must be provided: The -D FRU command may be followed with up to 16 device addresses. These device addresses are used to view up to 16 different FRU areas. The arguments following the "-D FRU" are in the same order and value as the NVS_TYPE, NVS_LUN, DEV_BUS and DEV_ADDRESS which may be found in the FRU file header of each FRU file. The LUN address is optional. If the LUN address is used, it must start with an 'L'. Usage: FRUSDR /d fru (device) [lun] (bus) (addr1) (addr2) (etc) Examples: 1. To display the server board SM BIOS area: C> FRUSDR /P /D SMB 2. To display the server board SDR's: C> FRUSDR /P /D SDR 3. To display the server board BMC FRU: C> FRUSDR /P /D FRU 4. To display the server board HSC1 FRU: C> FRUSDR /P /D FRU IMBDEVICE 00 C0 5. To display the server board HSC2 FRU: C> FRUSDR /P /D FRU IMBDEVICE 00 C2 Note: If your system does not display the above FRU device, then it probably does not contain that device. ---------------------------------------------------------------------------- TEMPORARY FILES ---------------------------------------------------------------------------- Temporary files are not created by default. If you desire to have temporary files created you must use the undocumented "/tmp" switch on the command line, then when the FRUSDR Loader is executed, it creates temporary files which may be used to aid in recreating a problem, should on arise. The FRUSDR Loader does not remove the temporary files, the temporary files may be erased by the user after the FRUSDR Loader has completed. ---------------------------------------------------------------------------- FRU FIELD LENGTHS ---------------------------------------------------------------------------- If a user is going to develop their own Configuration, FRU or SDR files, then they need a thorough understanding of FRU areas and lengths. That discussion is beyond the scope of this document. Although, only a basic understanding of how the FRUSDR application uses FRU files is needed before one modifies information in a FRU field via a configuration file prompt. The governing FRU format and SM BIOS specification documents do not specify a maximum FRU field length. However, a length constraint does exist due to the limited amount of space available in the Non-Volatile Storage device containing these items. These maximum lengths are artificial since, if all strings were of the maximum length, the FRU file would overflow the FRU area. Therefore, the true maximum field length is actually controlled by the space available to the FRU file. As a rule, the length defined in the header of the FRU file and the sizes defined in each FRU area of the FRU file must not be altered. These were originally chosen so that the FRU file would fit into the FRU area. Often each FRU area does contain a certain amount of padding, which will allow an increase in the length of some strings. To be on the safe side, if FRU strings are modified, they should be kept at the same length as the current string in that FRU area. For fields such as the Asset Tag, for which data may not exist to fill the field, the length should be kept to as few characters as needed, not to exceed 31 characters. ============================================================================= REFERENCE MATERIAL ============================================================================= Intel(R) Server Board SE7501BR2 Technical Product Specification (TPS) [END OF FRUSDR RELEASE NOTES] ============================================================================= ABOUT THIS HSC RELEASE ============================================================================= Firmware Version: 0.10 This document applies to the firmware used in the Hot Swap Controller of the Intel Server Chassis SC5200. H2FHxxxx.HEX is used by the FWPIAUPD utility to update the Hot Swap Controller (HSC) code on a running server. ============================================================================= SUPPORTED SYSTEMS ============================================================================= Intel Server Board SE7501BR2 ============================================================================= SYSTEM BIOS & FIRMWARE DEPENDENCIES ============================================================================= - None ============================================================================= IMPORTANT INSTALLATION NOTES ============================================================================= - Validation: Intel only validates system software releases that are current. System software is defined as BIOS, BMC firmware, and FRU/SDR. Intel does not perform regression testing of current system software with previous versions of system software. Intel recommends upgrading to the latest revisions of system software as necessary. There are no known compatibility issues or dependencies between system software revisions. ----------------------------------------------------------------------------- UPDATING THE FIRMWARE ----------------------------------------------------------------------------- The firmware is updated by the FWPIAUPD.EXE utility program that is included with this release package. This program can be run interactively (the program prompts the user for information) or with all information supplied on the command line. Using the command line is less prone to error, the command line to use is: FWPIAUPD -ni -u -o -[p|s] -nopc H2FHxxxx.HEX The notation -[p|s] means to include either the -p OR the -s, but not both. -p selects the primary HSC for updating, -s selects the secondary HSC for update (SC5200 HSRP Chassis only). In a system with only one HSC installed, that is the primary HSC, so all users will need to use the -p switch. If two HSCs (supporting up to 10 drives) are installed, the FWPIAUPD command will need to be run twice, once with -p and once with -s. The order they are run is not important. (There is no way to tell the utility to do both at once.) The supplied PRIUPDAT.BAT and SECUPDAT.BAT batch files update the primary and secondary HSCs using the command lines described above. ----------------------------------------------------------------------------- BOOT BLOCK UPDATES ----------------------------------------------------------------------------- The boot block on the HSC cannot be updated. Never use the -b or -boot switch on the command line. If the utility is run interactively, always answer NO to the "Update the boot block" question. If you do attempt to update the boot block, it will not be modified, that area of the flash chip is write-protected. However, when the utility attempts to verify that the code in the flash matches the code in the H2FHxxxx.HEX file, the verify will fail. Please note that this is a "false" warning - the boot block on the HSC is still perfectly fine since it is write-protected. The reason the verify fails in this case is that each version of firmware places a time/date stamp of when the firmware was compiled into the boot block area of the H2FHxxxx.HEX file. It is this data that changes with each new file and causes the verify to fail. ============================================================================= KNOWN ISSUES/WORKAROUNDS ============================================================================= - None. ============================================================================= FEATURES ADDED IN THIS RELEASE ============================================================================= - None. ============================================================================= ISSUES FIXED SINCE LAST RELEASE ============================================================================= - HSC did not handle SCSI messages that used multiple message bytes properly. This caused Linux install failures with certain RAID cards and Linux versions. HSC 10 corrects this. Note that the HSC doesn't support multi-byte messages, but it now rejects them correctly. - HSC firmware can be updated via server boards that do not support a Baseboard Management Controller. - To support BMC-less operation, the HSC now quits attempting to communicate with the BMC after 5 communication failures in a row, and declares that there are 0 monitorable power supplies. This allows SAF-TE communications to proceed. - HSC accepts all ACPI states define by IPMI 1.5. ============================================================================= REFERENCE MATERIAL ============================================================================= Intel(R) Server Platform SE7501BR2 Technical Product Specification (TPS) [END OF HSC RELEASE NOTES]