============================================================================= Intel(R) Server Board SE7501BR2 ============================================================================= INTEL Enterprise Platform & Services Marketing Intel Corporation 2111 N.E. 25th Avenue, Hillsboro, OR 97124 USA ============================================================================= DATE: April 7, 2005 TO: Intel server platform SE7501BR2 customers SUBJECT: Intel SE7501BR2 Production BIOS Release P23 (Build 0082) ============================================================================= LEGAL INFORMATION ============================================================================= Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Intel is a registered trademark of Intel Corporation. *Other names and brands are the property of their respective owners. Copyright (C) 2005 Intel Corporation. ============================================================================= ABOUT THIS RELEASE ============================================================================= Release # : P23 Version # : 23.00 Build # : 0081 Build Stamp : SBR20.86B.0082.P23.0504071730 Build Date : April 7, 2005 ============================================================================= BIOS COMPONENTS/CONTENTS ============================================================================= Processor supported: Intel(R) Xeon(TM) Processors with 512KB L2 Cache and Intel(R) Xeon(TM) Processors with 512KB L2 Cache and 1M L3 Cache. Microcode update versions: CPUID Microcode Stepping 0F24h 1F B0 0F27h 38 C1 0F29h 2D D1 0F25h 29 M0 System Hardware Configuration Supported: SE7501BR2 Production boards (A95686- 502 or later) ============================================================================= SYSTEM FIRMWARE REQUIREMENTS/REVISIONS ============================================================================= BMC FW : 1.17 or higher FRU/SDR : 5.5.J or higher HSC : 0.10 On-Board Component Option ROM Versions: Adaptec 7901 SCSI : 4.30S2 ATI Rage XL VGA : 09A Intel Pro/100 NIC : 4.1.16 Intel Pro/1000 NIC : 1.2.26 ============================================================================= INSTALLATION NOTES ============================================================================= IMPORTANT NOTES: 1. SE7501BR2 BIOS is not compatible with Windows 98 or Windows XP bootable diskettes. Please use DOS 6.22 booting diskette or ROM-DOS booting diskette. 2. Firmware must be updated before BIOS. If it isn't, the BIOS update may or may not work. Refer to the System Firmware Requirements section above. 3. CMOS should always be cleared after a BIOS update. But if your current BIOS version is newer than P08-0065, you don't need to clear CMOS because CMOS Map has not changed since then. UPDATE INSTRUCTIONS: This instructions do not apply when running the update directly from the Software Update Package Menu. In that event, instructions displayed in the screen should be followed. The instructions below only applies when creating a BIOS update disk. 1. Create a BIOS update disk; ensure to use a bootable floppy. 2. Boot the SE7501BR2 server board with floppy created in step #2. 3. At the DOS prompt type 1 (or 1.BAT) and press . The update will show two progress bars. After the second progress bar has reached 100 percent, the system will reboot (typically under 3 minutes). 4. Once the update is complete, proceed to clear CMOS. CLEARING CMOS: 1. Power down system and disconnect AC power. 2. Move the CMOS Clear jumper (J1H1) from BMC Control position (pins 1-2) to Force Erase position (pins 2-3). 3. Power up the system and allow BIOS to POST. A message will be displayed indicating "CMOS has been cleared by jumper". If applicable, enter BIOS setup by pressing F2 and change any BIOS user settings; press F10 to Save Changes and Exit. 4. Power down system and disconnect AC power. 5. Move the CMOS Clear jumper (J1H1) back to BMC Control position (pins 1-2). 6. Power up the system and boot normally. ============================================================================= KNOWN ISSUES/WORKAROUNDS ============================================================================= 1. With Intel(R) Xeon(TM) processors with 533MHz FSB, you must use DDR266 for all memory banks on a 533 system. 2. To enable PCI PERR logging, the user must enable "Assert NMI on PERR" in BIOS setup. 3. The clock to a PCI slot is turned off if no card is present in the slot. Port 80h cards are not considered valid PCI cards, thus if a Port 80h card is plugged into PCI slots 5 or 6 the last port 80h value that will be seen is F2h before the clock is turned off to these slots. A workaround to prevent the clocks from being turned off on PCI Slots 5 and 6 is to enable Num Lock under BIOS setup. 4. PCI-X clock speed: # Slots Channel Channel A Channel B Populated (AIC-7901) 0 PCI-X/100MHz PCI-X/133MHz 1 PCI-X/100MHz PCI-X/133MHz 2 PCI-X/100MHz PCI-X/100MHz ============================================================================= FEATURES ADDED ============================================================================= Build P22-0081: - None. Build P22-0081: - #20363 - Boot Agent Update to 1.2.26 & 4.1.16 New IBA binaries are included in this release - #20365 - Option To Include All Processor Threads In MP Table New Setup option, "HT Technology in MPS" was added to Processor menu. When it is enabled along with Hyperthreading, MPS table will have processor entries for hyperthreaded processors. Build P20-0079: - Added new microcode update for D1 stepping of Intel(R) Xeon(TM) processors with 512KB L2 Cache and M0 stepping of the Intel(R)Xeon(TM) processors with 512KB L2 Cache and 1MB L3 Cache. - Added routine to display the Product Manufacturer Name from the FRU to the top line of the POST Diagnostic screen. If the string (from the FRU) is read as Intel, only a blank line will be shown, if any other string is read it will be displayed. - Added the latest IBA 4.1.15 (Moab - 10/100) and 1.2.22 (Kenai32 - Gbit) Build P16-0075: - Added new microcode update for M0 stepping of the Intel(R)Xeon(TM) processors with 512KB L2 Cache and 1MB L3 Cache. Build P15-0074: - Added new microcode update for B0/D1 stepping of Intel(R) Xeon(TM) processors with 512KB L2 Cache and M0 stepping of the Intel(R)Xeon(TM) processors with 512KB L2 Cache and 1MB L3 Cache. - AIC-7901 SCSI option ROM 4.30S2 replaces previous version 4.10.03S2. Build P14-0073: - None. Build P13-0072: - Added new microcode update for C1/D1 stepping of Intel(R) Xeon(TM) processors with 512KB L2 Cache. - Added support for upcomming processor speeds. Build P12-0071: - None. Build reserved, not released to general public. Build P11-0070: - New microcode (revision 11) added to support the M0 stepping of the Intel(R) Xeon(TM) processors with 512KB L2 Cache and 1MB L3 Cache. - Added fix for MCH Errata3: System Hung After Asynchronous Reset To DIMM. Build P10-0068: - None. Build reserved, not released to general public. Build P09-0067: - None. Build reserved, not released to general public. Build P08-0065: - None. Build reserved, not released to general public. Build P07-0064: - None. Build reserved, not released to general public. Build P06-0063: - New microcode update (revision 0F) for D1 stepping of Intel(R) Xeon(TM) processors with 512KB L2 Cache was added. - SC1350 chassis 1U riser support is added. - AIC-7901 SCSI option ROM 4.10.03S2 replaces previous version 4.10.01S2. Build P05-0051: - As required in Intel?NetBurst(TM) Micro-Architecture BIOS Writer's Guide rev 1.6, BIOS P05 enables Machine Check Architecture handler. - 48-bit LBA mode is supported. This is done to support IDE hard drive sizes beyond the 128GB barrier. - New microcode update (revision 1D) for B0 stepping of Intel(R) Xeon(TM) processors with 512KB L2 Cache. Build P04-0047: - None. Build P03-0046 - SCM support was added. Build P02-0043: - Intel(R) E7501 Chipset memory reference code 1.01 was merged. ============================================================================= ISSUES FIXED ============================================================================= Build P22-0081: - #20528 - Adaptec SCSI Cards prevent entry to Setup This failure was actually caused by an error in the P21-0080 fix for Tracker #20063 BMC Timestamp fix. This error has been corrected. - #20367 - SMBIOS Onboard Devices FW Revs Incorrect This is trivial fix for option ROM versions. - #20364 - FP CMOS Clear BIOS Security Issues. Issue #1: Since: (A) anyone can walk up and do a CMOS Clear from the Front Panel, (B) even when the chassis is secured against intrusion and BIOS security settings are in effect, and (C) the FP CMOS Clear will reset the BIOS security settings without requiring a password or access to Setup -- resetting Boot Password, Secure Boot, etc, to defaults, and allowing boot access to alternate media and access to the keyboard and video -- the FP CMOS Clear represents a BIOS security exposure. The code was changed to recognize the FP CMOS Clear, as distinct from the physical CMOS Clear Jumper. In the case of CMOS Clear from the Front Panel, the BIOS Security settings on the Setup Security Screen (and a couple of others) will not be reset. This means that Boot Password, Secure Mode, and Secure Boot cannot be reset with a FP CMOS Clear, only with the CMOS Clear Jumper which is protected inside the chassis. The following BIOS security settings are preserved for FP CMOS Clear: FP Power Button Inhibit NMI Control AC Link (Powerfail) Policy Post Error Pause Boot Password Secure Boot Secure Mode Timeout Secure Mode Hotkey Video Blanking Floppy Drive Write Protect (OEM-specific visiblity) HDD Boot Sector Write Protect Issue #2: It is possible to do a Front Panel Clear even when the FP Power button is disabled and AC Link policy set to "Always Power On" -- by pulling the plug, and then holding in the power button when the AC power is restored. The system will halt and allow the FP buttons to be used to initiate FP CMOS Clear. This means there is no practical way to prevent a Front Panel CMOS Clear. The code was changed to check for CMOS Clear asserted by BMC for FP Clear when the CMOS Clear signal (GPIO) is asserted. If not FP Clear, logic continues to the normal "jumper" CMOS Clear. If CMOS Clear is FP Clear, then CMOS validity is checked. If CMOS is not valid (Diagnostic byte indicates battery fail and/or checksum error) then the code path goes to join the "bad CMOS" restore path. If CMOS is valid, the FP Power button setting is checked in CMOS. If the FP Power button is supposed to be disabled, then this is a bogus FP Clear. The BMC is commanded to deassert the signal, and the code path goes to join the "CMOS Clear not set" path. So for the case where the FP Clear is forced by some means in spite of the Power button being disabled, the FP CMOS Clear will be ignored. Issue #3: Even when BIOS Secure Boot is enabled so the Front Panel is locked to prevent the Power button from halting the system, and the AC Link (After Powerfail) setting is "Always Boot" so removing and restoring AC power will not leave the system halted, there is a small window of time immediately after the start of the boot before the Front Panel is locked into Secure Mode. During that time, the Front Panel Power button may be pressed to halt the system. Once the system has been halted, a Front Panel CMOS Clear can be performed to clear the BIOS security settings. This is fixed by the fixes to issues #1 & #2. Enabling the Front Panel Power Switch Inhibit will reduce the duration of the window of vulnerability, but per issue #2 a FP CMOS Clear is still possible. The fix for issue #2 will eliminate that possibility altogether if the FP Power Switch Inhibit is enabled, since an improper FP CMOS Clear will be rejected and deasserted. However, even if the FP Power Button is active and a FP CMOS Clear is performed, the fix for issue #1 means that the BIOS security settings cannot be cleared from the Front Panel. Issue #4: When the Windows Operating System performs a "Shutdown", it leaves the system halted with the Front Panel Power Button in a post-ACPI state. At that point, the Front Panel Power Button may be operated to performs a Front Panel CMOS Clear which will clear the BIOS security settings. This is fixed by the fixes to issues #1 & #2. The fix for issue #1 means that if the Front Panel Power Button Inhibit is set, a Front Panel CMOS Clear from the Shutdown state will be rejected and dismissed. If the FP Power Button is operative, the fix to issue #2 means that the BIOS security settings cannot be cleared from the Front Panel. Issue #5: The password status tokens were improperly getting reset by CMOS Clear, although the passwords themselves were intact. The visible effect of this was that the SMBIOS table was incorrect after a CMOS Clear. For any CMOS Clear, the password status tokens are preserved, as is the Setup Access Level setting. Issue #6: When CMOS is found to be invalid/corrupt, CMOS is cleared and the normal default settings are restored. However, the passwords, possibly corrupt if CMOS is corrupted, were not cleared. For the case where CMOS is invalid/corrupt, the password fields will be cleared. Password status tokens will also not be preserved. Build P21-0080: - #20063 - BIOS sets BMC Timestamp incorrectly one day behind. BIOS was calculating the 32-bit BMC timestamp incorrectly by one day for synchronization at boot, resulting in BMC date one day behind system date as recorded in SEL entries. This calculation has been corrected. - #19540 - Windows 2003 Server Device Manager shows only two processors in a dual processor HyperThreaded system. This was due to mismatch in Processor IDs between the Processor and Local APIC definitions. These ID's have been changed to match. Build P20-0079: - Tracker 15942 / 16638 / 15894 -- Make cache line size register (0Ch) have a value of 08h for add in cards as well. - Tracker 15783 -- System hangs when NIC cable is removed in DOS. Clears the LAN interrupts before Int19, after the LAN console was disabled (kill_LAN_Stack). - Tracker 17076 / 17077 -- Add new Prestonia CPU Patches for D1 (M02F2922) and M0 (M01F251E) steppings to address errata P72. - Tracker 18708 / 18746 / 18748 -- Add new Prestonia CPU Patches for D1 (M02F292D) and M0 (M01F2529) steppings to address errata P76. - Tracker 18184 -- Boot Support from PQI Secure DOM Required in Harlingen BIOS. - Tracker 18186 -- The current state field of each PCI-X is reported as 'unknown' (instead of 'in use' or 'available' depending on the presence of a PCI card in the corresponding slot). Build P19-0078: - Trackers 16625 -- [x] Post Code#8101- Processor 2 failed BIST reported without CPU#2 installed Not rootcaused yet. Added workaround to reset the system if invalid CMOS values are set. Build P17-0076: - Trackers 15713 / 14906 -- NEC Logo and SLP Key Lost User Logo lost during boot. This was caused by a failure in the Fault Tolerant Update. The failure has been corrected. - Tracker 15113 -- NEC SMI Timeout issue Bryson SMI fix added: re-issue the software SMI if it does not get serviced the first time. Shut off USB Legacy SMI generation when save and exit is chosen from setup. This stops the SMI hang that occurs when leaving setup. Build P16-0075: - Improper Bridge Initialization via BIOS Creating Severe I/O Bottleneck. Fixed by changing the P64H2 (both devices -- 29 and 31) cache line size register (0Ch) from a value of 10h to a value of 08h. This fix will dramatically speed up the PCI performance numbers as well. - PXE-E01 message reported when Onboard NIC is disabled. Fixed by skipping LAN console in dih_sys_config_done and skipping kill_lan_stack routine at the end of POST if NIC is disabled. Build P15-0074: - Ghost PCI slot 2 when a 1U riser is plugged in on Bryson/Kahana system. Fixed by placing a value in the FRU which the BIOS could read to determine if a 1U or 2U riser is present. - No AC-Link Parameter Option Available In BIOS Setup. Fixed by removing Externalfunction=check_sysbmc_proc2 from Q_POWER_FAILURE_OPTION declaration. - BIOS version information in W2K Advanced server is incorrect. Fixed by using ax instead of eax during analyzing BIOS version string. - Boot from USB devices works when Legacy USB set as KB only or KB and Mouse. Fixed by checking for Q_USB_LEGACY_ENABLE CMOS token and enumerating USB mass storage device only if the value of this token is set to "Auto". - Add "S" (SCSI SKU) or "D" (SCSI Depop) to end of SMBIOS Type 2 Product field. - With failed DIMM, incorrect errors are displayed in POST and SEL. Fixed by adding single channel support codes to the following two procedures: get_failing_memory_socket_jmp_di, get_failing_memory_address_jmp_di. - SuSE 8.2/9.0 fails with HostRAID configuration on Bryson. Fixed by replacing previous AIC-7901 SCSI option ROM version 4.10.03S2 with 4.30S2. Build P14-0073: - Fixed improper L3 Cache Initialization which was leading to power cycling failures. Build P13-0072: - 3.06Ghz/533FSB M0 CPU power cycle failure exhibited in stress testing. - Invalid SMBIOS structure implementation for processors without L3 cache. - ERROR! 8193: displayed on systems configured with valid D1 & M0 mixed processor steppings. - BIOS logo incorrectly displayed after CMOS clear. - Corrected issue with certain ATAPI Tape Drives not working on U-DMA mode. Build P12-0071: - None. Build reserved, not released to general public. Build P11-0070: - POST error pause exhibited when system configured with ? mixed CPU stepping - DIMM error occurred on POST with certain 1GB DIMMs during AC or DC cycling test Build P10-0068: - None. Build reserved, not released to general public. Build P09-0067: - None. Build reserved, not released to general public. Build P08-0065: - None. Build reserved, not released to general public. Build P07-0064: - None. Build reserved, not released to general public. Build P06-0063: - Failed to create Service patition in USB HDD - Setting DAY field only in BIOS Setup after Battery reset results 01/01/1990 on next boot - Error message for memory configuration are different between FSB 400 MHz and 533 MHz. - Flash Update driver won't load under Microsoft Windows* with latest Bryson BIOS release Build P05-0051: - Netburst BWG rev 1.6 requires BIOS to implement an MCA handler. - Does not wake with Legacy Wake On LAN/PME/WOR, after told to go to standby from the Windows 2000 Start Task Bar Menu. - SEL log fills with single bit errors if extended memory test is enabled and there is a failing DIMM in xB. - Need BIOS support for 48-bit LBA to enable compatibility with IDE drives greater than 128GB in size. - Double bit errors logged in SEL or displayed in POST Error messages do not fully meet specification. - No SEL event is logged when settings are changed and saved in BIOS SETUP - When "Reset Config Data" in BIOS SETUP is selected, the "System Reconfigured" SEL event continues to be logged on subsequent boots. - After setting Serial Port Address to "disabed", "Redirection Port" is incorrect. - NIC2 can not PXE Boot if the higher device in boot priority has an active LAN connection. - Wake on PME by PCI Slot5/6 does not work correctly. - Late post FRB does not "Stay On" or "Power Off". - Support the second OEM Strings of DMI Type 11. - Unreported I/O test failure with Microsoft Windows* Server 2003. - System hangs during post with six FC adapters in PCI slots. - Ensure proper SCSI vendor/device ID in the SCSI PCI config space based on AIC-7901 with raid or without raid. - ACPI Errors test failure issue with Windows Server2003 HCT11.1. Build: P04-0047 - Proprietary 33 MHz PCI card not functional in PCI-X slots. - Exiting BIOS Setup after Front panel CMOS clear system prompts for power off. - Hard Disk Pre-Delay option of BIOS Setup doesn't work. - Can't detect SD-C2612 DVDROM and IDE HD on the same IDE channel. - USB LS120 will not read or write to a 1.44Mb floppy disk while booted to DOS. - Option ROM Disable in BIOS 20 Setup does not work with "bridged" adapters. - BIOS does not lock down the primary flash partition at the end of POST. - PCI BIOS function call GET_INT_ROUTE (0x0e) fails with a page fault. Build P03-0046 - Certain Serial Event Logs are not generated. - Setup Viewer I/F incorrect. - Few words in BIOS setup do not have foreign translations. - BMC asserts the CMOS clear request after Front Panel CMOS Clear. - Disabling NIC1 causes the W2K Found New Hardware Wizard to request SCSI drivers. Build P02-0043: - Need to update BIOS to memory reference code 1.01 - PS/2 keyboard not working in top PS/2 port when no PS/2 mouse is present - When CMOS is Cleared, DIMM BANK #1 & #2 information is set to Not Installed. - No POST error is displayed when configuring system with mismatch CPU speeds - When FRB Policy is set to "Retry 3 Times" in SETUP, the system does not work. - With only 1 Bank populated the system does not recognize SBE or DBE's - Events continue to be logged when Event Logging is disabled - Need to change MAX length of strings for DMI Type1 - Auto-rebooting running OB SCSI option ROM due to "Watchdog timer failed" - BIOS does not display the FSB speed during POST - POST displays "Legacy USB enabled" when USB Function is disabled ============================================================================= REFERENCE MATERIAL ============================================================================= Intel(R) Server Platform SE7501BR2 Technical Product Specification (TPS) [END OF RELEASE NOTES]