============================================================================= Intel(R) Server Board SE7501HG2 BIOS RELEASE NOTES ============================================================================= INTEL Enterprise Platform & Services Marketing Intel Corporation 2111 N.E. 25th Avenue, Hillsboro, OR 97124 USA ============================================================================= DATE: November 7, 2005 TO: Intel Server Board SE7501HG2 Customers SUBJECT: BIOS Release Notes: Production BIOS Release P22 (build 00060) ============================================================================= Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information dos not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Intel is a registered trademark of Intel Corporation. *Other names and brands are the property of their respective owners. Copyright (C) 2005 Intel Corporation. ============================================================================= ABOUT THIS RELEASE ============================================================================= Release # : P22 Version # : 22.00 Build # : 0060 Build Stamp : S7501HG0.86A.0060.P22.0504081437 Build Date : 8 April 2005 ============================================================================= BIOS COMPONENTS/CONTENTS ============================================================================= Processors supported: Intel(R) Xeon(TM) Processors with 512KB L2 Cache and No L3 Cache, 1M L3 Cache, or 2M L3 Cache. Microcode update versions: CPUID (Stepping) Microcode Rev. ----- ---------- -------------- 0F24h (B0) 1F (M02F241F) 0F27h (C1) 38 (M02F2738) 0F29h (D1) 2D (M02F292D) 0F25h (M0) 29 (M01F2529) System Hardware Configurations Supported: A95718-303 (or Higher) ============================================================================= SYSTEM FIRMWARE REQUIREMENTS/REVISIONS ============================================================================= BMC FW : 0017 (or higher) for A95718-303 (or higher) FRU/SDR : HG.5.5.I (or higher) for A95718-303 (or higher) HSC : 0.10 On-Board Component Option ROM Versions: -------------------------------------- SCSI Controller : Adaptec 7902 : 4.30S2 for A4 stepping Adaptec 7902 : 41003S2 for B0 stepping Video Controller : ATI Rage XL : 09A GR 4.332 NIC Controller : Intel 1.0Gb : 1.2.26 ============================================================================= IMPORTANT INSTALLATION NOTES ============================================================================= IMPORTANT NOTES: 1. CMOS should always be cleared after a BIOS update. 2. SE7501HG2 BIOS Update is not compatible with Windows 98 or Windows XP bootable diskettes. Please use a DOS 6.22 bootable diskette or a ROM-DOS bootable diskette. 3. Firmware must be updated before BIOS. If it is not, the BIOS update may not work. Refer to the System Firmware Requirements section above. UPDATE INSTRUCTIONS: These instructions do not apply when running the update directly from the Software Update Package Menu. In that case, instructions displayed on the screen should be followed. The instructions below only apply when updating from a BIOS update disk. 1. Note the settings of the SETUP parameters. Do this as a safety measure even if you do not intend to clear CMOS. Enter SETUP by hitting the F2 key during boot. Write down the settings for all Setup parameters, so that at the end of the BIOS update process you can restore them. 2 Download the BIOS from the Intel Support website. Insert a bootable diskette into drive "A:". Unzip the contents to expand the BIOS onto the bootable floppy in "A:". 3. Place the bootable floppy containing the BIOS into drive "A:" of the system that you want to upgrade, and boot the system from the diskette drive. 4. Update with the IFLASH program -- it is HIGHLY recommended that you update the BootBlock as well as the BIOS> 4.1 Type 1 at the DOS prompt BIOS option menu to update both automatically. -or- 4.2 Type 2 to start IFLASH in interactive mode. Update and reboot the system by following the menu prompts in IFLASH. The interactive mode allows you to update the User Logo or User Binary area, if necessary. (You'll know if you need to do this!) 5. The update will show two progress bars, one after the other. DO NOT DO ANYTHING TO INTERRUPT THE UPDATE! After the second progress bar has reached 100 percent, the system will reboot (typically under 3 minutes). 6. Once the update is complete, proceed to clear CMOS if you plan to do so. Then enter Setup by pressing the F2 key during boot up. Once in Setup, you can press the F9 to set the parameters back to default values. Re-enter the values you wrote down at the beginning of this process. If you do not set the CMOS values back to defaults using the F9 key or by clearing CMOS, the system may behave erratically if the CMOS layout has changed in the new BIOS version. NOTE: You may encounter a CMOS Checksum error or other problem after reboot. Try shutting down the system and booting up again. CMOS checksum errors require that you enter Setup, check your settings, save your settings with F10, and exit Setup. CLEARING CMOS (JUMPER): 1. Power down the system and disconnect AC power. 2. Move the CMOS Clear jumper (J1H1) from BMC Control position (pins 1-2) to the Force Erase position (pins 2-3). 3. Power up the system and allow BIOS to boot. A message will be displayed indicating "NVRAM Cleared by Jumper". If applicable, enter BIOS Setup by pressing F2 and change any BIOS user settings; press F10 to Save Changes and Exit. 4. Power down the system and disconnect AC power. 5. Move the CMOS Clear jumper (J1H1) back to BMC Control position (pins 1-2). 6. Power up the system and boot normally. CLEARING CMOS (FRONT PANEL): 1. Press and hold the front panel reset button for 4+ seconds. 2. Continue to hold the reset button and press the front panel power button 3. Release the reset and power button at the same time. 4. The server board will appear to boot in a normal manner but should display an "NVRAM Cleared by BMC" message during the boot. ============================================================================= BIOS RECOVERY NOTES ============================================================================= 1. BIOS Recovery requires that you have a copy of the BIOS on a diskette, prepared the same way as for a normal update. 2. Power down the system and disconnect AC power. Move the BIOS Recovery Jumper (J1H1) from the normal position (pins 9-10) to the Recovery position (pins 10-11). 3. Place the BIOS Update diskette in drive "A:", reconnect power and boot the system. 4. As the system begins to boot, you will hear one BEEP. There will be no display. DO NOT INTERRUPT THE RECOVERY. At the end of recovery, there will be a double BEEP indicating success. 5. Power down the system and disconnect AC power. Move the BIOS Recovery Jumper (J1H1) back to the normal position (pins 9-10). 6. Reconnect power and boot normally. ============================================================================= KNOWN ISSUES/WORKAROUNDS ============================================================================= 1. With Intel(R) Xeon (TM) 533MHz FSB processors you must use DDR266 for all memory banks on an A95718-303 (or higher) system. 2. To enable PCI PERR logging, the user must enable "Assert NMI on PERR" in BIOS Setup. 3. The clock to a PCI slot is turned off if no card is present in the slot. Port 80h POSTcode debug cards are not considered valid PCI cards. For users who want to use a POSTcode debug card, please do the following: A. Install POSTcode debug card in slot 6. No other slot may be used. B. Enter BIOS Setup and go to the "Advanced" menu. Enable "NumLock" option to unconditionally enable the PCI clock for slot 6. 4. PCI-X clock speed is dependent on the BIOS Setup option to enable or disable the Onboard NIC in "Advanced" menu -> "PCI Configuration" -> "Onboard NIC". A. When Onboard NIC is set to Disabled: PCI-X Bus Mode/Frequency: # Slots Populated Channel A** Channel B** ----------------- ----------- ----------- 0 100MHz 133MHz 1 100MHz 133MHz 2 100MHz -N/A- B. When Onboard NIC is set to Enabled: PCI-X Bus Mode/Frequency # Slots Populated Channel A** Channel B** ----------------- ----------- ----------- 0 100MHz 100MHz 1 100MHz 100MHz 2 100MHz -N/A- ============================================================================= ========================== ABOUT THIS RELEASE =========================== ============================================================================= P22-0060 Production Release: [Build Stamp S7501HG0.86A.0060.P22.0504081437] --Features Added: [1] BIOS ID updated to Production Release P22-00060. --Issues Resolved: [2] Error in BMC Timestamp Fix Caused Memory Corruption - Problem was a failure in the fix for the BMC Timestamp problem in P2-0058. Failure was corrected. --Features Removed: -None- ============================================================================= ======================== PREVIOUS RELEASES ============================== ============================================================================= P21-0059 Production Release: [Build Stamp S7501HG0.86A.0059.P21.0503300929] --Features Added: [1] New Setup option To Include All Processor Threads In MP Table, "HT Technology in MPS" was added to Processor menu. When it is enabled along with HyperThreading, the MPS table will have processor entries for secondary processor threads in HyperThreaded processors. --Issues Resolved: [2] SMBIOS onboard devices FW revs incorrect. SMBIOS table is updated to have correct FW version information for Intel Boot Agent and SCSI. [3] Front Panel CMOS Clear resets BIOS security settings without password. In addition, it was possible to do a Front Panel CMOS Clear even when the FP Power Button was disabled and/or Secure Boot was enabled and A/C was set to "Always On", following either a Windows Shutdown or and A/C power failure (or unplugging the power supply). The power-on vulnerability has been fixed, and now the FP CMOS Clear is not allowed to reset the BIOS Security settings for the following options (CMOS Clear by jumper will reset these settings): FP Power Button Inhibit NMI Control AC Link (Powerfail) Policy Post Error Pause Boot Password Secure Boot Secure Mode Timeout Secure Mode Hotkey Video Blanking Floppy Drive Write Protect (OEM-specific visibility) HAD Boot Sector Write Protect ============================================================================= P20-0058 Production Release: [Build Stamp S7501HG0.86A.0058.P20.0503272322] --Features Added: -None- --Issues Resolved: [1] BIOS sets BMC Timestamp incorrectly one day behind. The BIOS was calculating the 32-bit BMC timestamp incorrectly by one day for synchronization at boot, resulting in the BMC date as recorded in SEL entries being set one day behind the system date. This calculation has been corrected. The incorrect date in the SEL timestamps was the only system impact. ============================================================================= P19-0057 Production Release: [Build Stamp S7501HG0.86A.0057.P19.0412221812] --Features Added: [1] Added Latest IBA Version 1.2.26 for GBIT NIC. --Issues Resolved: [2] Win2K3 shows physical CPU's in Device Manager only. An error in the processor numbering (a disagreement between two ACPI tables) caused this problem. ============================================================================= P18-0056 Production Release: [Build Stamp S7501HG0.86A.0056.P18.0409231600] --Features Added: [1] Added Latest IBA Version 1.2.22 for GBIT NIC. [2] Added new processor microcode updates for D1 (M02F292D) and M0 (M01F2529) processor steppings to address Xeon Processor Erratum P76. --Issues Resolved: -None- ============================================================================= P17-0055 Production Release: [Build Stamp S7501HG0.86B.0055.P17.0408240946] --Features Added: -None- --Issues Resolved: [1] The current state field of each PCI-X slot is reported as "Unknown" instead of "in use" or "available" depending on the presence of a PCI card in the corresponding slot. ============================================================================= P16-0054 Production Release: [Build Stamp S7501HG0.86B.0054.P16.0408091908] --Features Added: [1] Added Latest IBA Version 1.2.19 for GBIT NIC. [2] Added new processor microcode updates for D1 (M02F2922) and M0 (M01F251E) processor steppings to address Xeon Processor Erratum P72. [3] Added INT 19h Boot Support for PQI Secure Disk On Module (DOM). --Issues Resolved: [4] OEM User Logo and MS SLP Key lost during boot. This was caused by a failure in the Fault Tolerant Update for Flash memory. The failure has been corrected. [5] SMI Timeout fix added: re-issue the software SMI if it does not get serviced the first time. Also shut off USB Legacy SMI generation when "Save and Exit" is chosen from Setup. This avoids an SMI hang that can occur when exiting from Setup. [6] System hangs when NIC cable is removed in DOS. Fix clears the LAN interrupts before INT 19h boot, after the LAN console has been disabled. [7] Post Error Code #8101 "Processor 2 failed BIST" reported without CPU#2 installed. Fix suppresses error report generated for processor is which is not installed. ============================================================================= P15-0053 Production Release: [Build Stamp S7501HG0.86B.0053.P15.0405051201] --Features Added: -None- --Issues Resolved: [1] Make cache line size register (0Ch) have a value of 08h for add-in PCI cards as well as PCI-PCI bridges. This was a follow-up to an earlier performance-related fix for PCI-PCI bridge configuration (see P13 Release Notes for details). ============================================================================= P14-0052 Production Release: [Build Stamp S7501HG0.86B.0052.P14.0403310758] --Features Added: [1] Added BIOS functionality to display the Product Manufacturer Name from the FRU to the top line of the POST Diagnostic Screen, which is also the text-mode display when Serial Console Redirection is active. If the string (from the FRU) is read as “Intel”, only a blank line will be shown, but if any other Manufacturer Name string is read, it will be displayed. --Issues Resolved: -None- ============================================================================= P13-0051 Production Release: [Build Stamp S7501HG0.86B.0051.P13.0403080922] --Features Added: [1] Added new processor microcode updates for B0 (M02F241F), D1 (M02F2918), and M0 (M01F251A) processor steppings. [2] Added updated Adaptec SCSI Option ROM version 4.30S2 for A4 stepping of Adaptec SCSI controller. Note that the B0 stepping of the SCSI controller continues to use version 41003S2. --Issues Resolved: [2] BIOS version information in W2K Advanced server is incorrect. [3] Boot from USB devices works even when Legacy USB is set as KB only, or KB and Mouse only. [4] SuSE 8.2 and 9.0 fail in a HostRAID configuration. BIOS needs to use updated Adaptec SCSI Option ROM version 4.30S2 for A4 stepping of SCSI controller -only-. B0 Stepping continues to use version 41003S2. [5] Incorrect "bad DIMM" marking in single channel memory configuration. Wrong DIMM marked as "failed". [6] Improper Bridge Initialization via BIOS Creating Severe I/O Bottleneck. An I/O bottleneck was found at around 380 MB/s with multifunction fibre channel adapters. This performance issue has been identified as a limitation of the Intel 21154BE PCI-to-PCI bridge. BIOS normally programs the Cache Line Size register to 0x10 (64 Bytes). There is a limitation of the 21154BE bridge which states, "For a cache line size of 16 DWords, the 21154 disconnects a memory write and invalidate transaction on every cache line boundary". This means the that when a 2K Fibre Channel frame is received, it will get chopped up into 32 transfers on the host PCI bus. This fix changes the value set in the Cache Line Size register to 0x08 (32 Bytes), so the 21154BE bridge can hook up and transfer data in a pass-through mode, allowing for a higher utilization of the PCI bus, increasing the overall performance of the adapter. [7] PXE-E01 error message reported in POST, even when Onboard NIC has been disabled. ============================================================================= P12-0050 Production Release: [Build Stamp S7501HG0.86B.0050.P12.0312291655] --Features Added: [1] Added AC-Link parameter option, available in BIOS Setup under the "Server" menu. This allows control of the system behavior at powerup, after A/C power has been interrupted. This was necessary to allow the system to restart properly when A/C power is restored after a graceful shutdown by a UPS system. The standard "Last State" in that case would be "Off" instead of "On". --Issues Resolved: [2] Ghost PCI Slot #2 reported when using a 1U Riser in an SE7501HG2 system with a SR1350-E (Kahana) rackmount chassis. ============================================================================= P11-0049 Production Release: [Build Stamp S7501HG0.86B.0049.P11.0311131459] --Features Added: -None- --Issues Resolved: [1] Improper L3 Cache Initialization caused hangs on repeated power cycling. L3 cache handling has been modified to correct this. [2] 3.06 GHz Xeon Processor has an IERR fault when 1M L3 Cache is enabled. ============================================================================= P10-0048 Production Release: [Build Stamp S7501HG0.86B.0048.P10.030902] --Features Added: [1] Added new processor microcode updates for C1 (M02F2738) and D1 (M02F2915) processor steppings. [2] Added support for anticipated processor speeds at 3.2 GHz, 3.4 GHz. --Issues Resolved: [3] Corrected POST Error 8193: Processor steppings are different. [4] BIOS logo incorrectly displayed when many IDE and/or USB devices are installed. Too many lines displayed in the background caused scrolling, which removed the logo display. [5] Improper L3 Cache initialization corrected. [6] Incorrect SMBIOS Cache Reference when L3 cache is absent. [7] Sony SDX-420C & SDX-520C ATAPI Tape Drives cannot work in U-DMA, only PIO mode. ============================================================================= P09-0047 Production Release: [Build Stamp S7501HG0.86B.0047.P09.0307011125] --Features Added: [1] Added new processor microcode update for M0 (M01F2511) processor stepping. --Issues Resolved: [2] Support of M0 stepping processors with/without L3 cache fixed. [3] POST error pause with mixed CPU steppings. [4] DIMM error occurred on POST with Samsung 1GB during AC or DC cycling test. [5] Fix for MCH Errata3 -- system hung after asynchronous reset to DIMM. ============================================================================= P08-0045 Production Release: [Build Stamp S7501HG0.86B.0045.P08.0306141020] --Features Added: [1] Support of M0 stepping processors with/without L3 cache. First support for L3 cache on Prestonia processors. [2] Added new processor microcode update for M0 (M01F250D) processor stepping. --Issues Resolved: [3] POST error pause with mixed CPU steppings fixed for M0 F25 CPU ID, to allow +/- one stepping. ============================================================================= P07-0043 Production Release: [Build Stamp S7501HG0.86B.0043.P07.0305281010] --Features Added: [1] Added new processor microcode update for D1 (M02F290F) processor stepping. [2] Added support for 1U riser in SR1350-E (Kahana) rackmount chassis. [3] AIC-7902 SCSI Option ROM 4.00.03S2 replaces previous option ROM version 4.00.01S2. --Issues Resolved: [4] Flash Update driver would not load on Windows with latest SE7501HG2 BIOS release. [5] POST Error Messages for memory configuration are different between FSB 400 and 533. [6] Virtual LCD Message requirements. [7] BIOS version information is incorrect in W2K Advanced Server. [8] Failed to create Service Partition on USB HDD. [9] Unable to boot to service partition Win2K. [10] PERRs/SERRs on TIGPR2U/SE7501WV2 with 5V Riser Card and Gbit Ethernet Adapters (general PCI fix). [11] Setting DAY field only in BIOS Setup after Battery reset results in 01/01/1990 date on next boot. ============================================================================= P06-0035 Production Release: [Build Stamp S7501HG0.86B.0035.P06.0304161028] --Features Added: [1] Added new processor microcode update for B0 (M02F241D) processor stepping. [2] As required in Intel(R) NetBurst(TM) Micro-Architecture BIOS Writer’s Guide rev 1.6, enable Machine Check Architecture handler. [3] Add support for 48 bit LBA mode. This is required to support IDE HDD sizes beyond 137 GB. [4] Add SCSI Option ROM version 41003S3 for Adaptec AIC-7902 B0 stepping. --Issues Resolved: [5] With 6 FC adapters in PCI slots, system hangs during POST. [6] SubSystem ID for 7902 HostRAID mode is FFFF - should be 3424. [7] BIOS P04 Build 27 doesn't update the SSID section of the HostRAID SEEPROM. [8] LCD support for specific OEM -- remove the check for which BMC is loaded, send BMC commands for LCD regardless of which BMC is loaded. [9] WHQL HCT 11.1 Unreported Memory and IO Ports fails with WinSrv 2003. [10] Does not wake with Legacy Wake On LAN/PME/ WOR, after shutting from Win2K menu. [11] SEL log fills with SBE if extended memory test is enabled & failing DIMM in xB. [12] DBE's not logged properly in SEL or POST error messages. [13] When changing BIOS Setup settings and "Exit Saving Changes", the SEL Event "System Reconfigured" is not logged. [14] When "Reset Config Data" is selected in BIOS Setup, the SEL Event "System Reconfigured" continues to be logged every time the system resets. [15] After setting Serial Port Address to "disabled" in Setup, "Redirection Port" is incorrect. [16] NIC2 cannot PXE Boot if a device higher in boot priority is connected. [17] Wake on PME by PCI Slot5/6 does not work. [18] Late POST FRB does not "Stay On" or "Power Off", always resets. [19] Need to support 2nd instance of SMBIOS Type 11 OEM Strings. [20] Unreported I/O test failure with Windows Server2003. [21] ACPI Errors cause test failure with Windows Server2003 HCT 11.1. ============================================================================= P05-0033 Production Release: [Build Stamp S7501HG0.86B.0033.P05.0303171632] --Features Added: [1] New MCH reference code Rev 1.02: ODT (enable/disable) with write ring-back support. --Issues Resolved: -None- ============================================================================= P04-0027 Production Release: [Build Stamp S7501HG0.86B.0027.P04.0301301029] --Features Added: [1] Single channel memory support added. [2] New processor microcode revision 34 for C1 stepping processors. --Issues Resolved: [3] Proprietary 33 MHz PCI card not functional in Bryson PCI-X slots. [4] Exiting BIOS Setup after Front panel CMOS clear, system prompts for power off. [5] Hard Disk Pre-Delay option of BIOS Setup doesn't work. [6] Can't detect SD-C2612 DVDROM and IDE HD on the same IDE channel. [7] USB LS120 will not read or write to a 1.44Mb floppy disk while booted to DOS. [8] Option ROM Disable in BIOS 20 Setup does not work with "bridged" adapters. [9] BIOS does not lock down primary flash partition at the end of POST. [10] Setup Viewer interface incorrect. [11] A few words in BIOS setup do not have foreign translations. [12] Disabling NIC1 causes the W2K Found New Hardware Wizard to request SCSI drivers. [13] BMC is still asserting the CMOS clear request after Front Panel CMOS Clear. [14] POST displays "Legacy USB enabled" when USB Function is disabled. [15] Need to change MAX length of strings for SMBIOS Type 1. [16] Multiple customers requesting that BIOS display the FSB speed during POST. [17] PCI BIOS function call GET_INT_ROUTE (0x0e) fails with a page fault. ============================================================================= P03-0024 Production Release: [Build Stamp S7501HG0.86B.0024.P03.0301071022] --Features Added: [1] New video Option ROM for EMI noise reduction, uses 100MHz clock for video memory. --Issues Resolved: -None- ============================================================================= P02-0023 Production Release: [Build Stamp S7501HG0.86B.0023.P02.0301031126] --Features Added: [1] Single channel memory support was added. [2] New video option rom for EMI noise reduction, uses 100MHz clock for video memory. [3] New CPU microcode patch to support 2.8MHz performance issues. BIOS change necessary to set bit 23 of the IA32_MISC_ENABLE MSR register. --Issues Resolved: [4] Some SEL event messages are not generated. [5] Setup Viewer interface incorrect. [6] A few words in BIOS setup do not have foreign translations. [7] Disabling NIC1 causes the W2K Found New Hardware Wizard to request SCSI drivers. [8] BMC is still asserting the CMOS clear request after Front Panel CMOS Clear. [9] POST displays "Legacy USB enabled" when USB Function is disabled. [10] Need to change MAX length of strings for SMBIOS Type 1. [11] Multiple customers requesting that BIOS display the FSB speed during POST. ============================================================================= P01-0020 Production Release: [Build Stamp S7501HG0.86B.0020.P01.0212061444] ------------------------------ --Initial Production Release-- ------------------------------ --Features Added (from Beta Release): [1] E7501 memory reference code 1.01 was merged. --Issues Resolved (from Beta Release): [2] Need to update BIOS to memory reference code 1.01. [3] PS/2 keyboard not working in top PS/2 port when no PS/2 mouse is present. [4] When clearing CMOS, BANK#1/#2 information is set to "Not Installed". [5] System does not perform POST error pause for SBE/DBE. [6] BIOS setup shows Core to Bus ratio, and option is functional. ============================================================================= REFERENCE MATERIAL ============================================================================= Intel(R) Server Platform SE7501HG2 Technical Product Specification (TPS) [END OF RELEASE NOTES]